full_adder.v

@@ -23,9 +23,6 @@ module FULL_ADDER(S,CO,A,B, CI);
 output S,CO;
 input A,B, CI;
 
-wire Y, CO1, CO2;
-HALF_ADDER ha1(.Y(Y), .C(CO1), .A(A), .B(B));
-HALF_ADDER ha2(.Y(S), .C(CO2), .A(Y), .B(CI));
-or (CO, CO1, CO2);
+//TBD
 
-endmodule
+endmodule;

half_adder.v

@@ -22,7 +22,6 @@ module HALF_ADDER(Y,C,A,B);
 output Y,C;
 input A,B;
 
-xor digit(Y, A, B);
-and carry(C, A, B);
+// TBD
 
-endmodule
+endmodule;

logic.v

@@ -20,7 +20,7 @@ output [63:0] Y;
 //input list
 input [63:0] A;
 
-RC_ADD_SUB_64 twoscomp64_sub(.Y(Y), .A(64'b0), .B(A), .SnA(1'b1));
+// TBD
 
 endmodule
 
@@ -31,7 +31,7 @@ output [31:0] Y;
 //input list
 input [31:0] A;
 
-RC_ADD_SUB_32 twoscomp32_sub(.Y(Y), .A(0), .B(A), .SnA(1'b1));
+// TBD
 
 endmodule
 
@@ -143,4 +143,4 @@ input [1:0] I;
 
 // TBD
 
-endmodule
+endmodule

rc_add_sub_32.v

@@ -29,21 +29,7 @@ input [63:0] A;
 input [63:0] B;
 input SnA;
 
-// carry-in bits for each 1-bit full adder
-wire C[0:64];
-buf (C[0], SnA);
-
-genvar i;
-generate
-    for (i = 0; i < 64; i = i + 1)
-    begin : add64_gen_loop
-        wire B_xor;
-        xor (B_xor, B[i], SnA);
-        FULL_ADDER add64_inst(Y[i], C[i+1], A[i], B_xor, C[i]);
-    end
-endgenerate
-
-buf (CO, C[64]);
+// TBD
 
 endmodule
 
@@ -56,20 +42,7 @@ input [`DATA_INDEX_LIMIT:0] A;
 input [`DATA_INDEX_LIMIT:0] B;
 input SnA;
 
-// carry-in bits for each 1-bit full adder
-wire C[0:32];
-buf (C[0], SnA);
-
-genvar i;
-generate
-    for (i = 0; i < 32; i = i + 1)
-    begin : add32_gen_loop
-        wire B_xor;
-        xor (B_xor, B[i], SnA);
-        FULL_ADDER add32_inst(Y[i], C[i+1], A[i], B_xor, C[i]);
-    end
-endgenerate
-
-buf (CO, C[32]);
+// TBD
 
 endmodule
+