project: minor refactors
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E0EBF441EA424369
@ -1,13 +0,0 @@
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// memory data file (do not edit the following line - required for mem load use)
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// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m
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// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
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00000000
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// memory data file (do not edit the following line - required for mem load use)
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// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m
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// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
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0000000a
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0000000b
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0000000c
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0000000d
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0000000e
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0000000f
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00000010
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00000011
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00000012
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00000013
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// memory data file (do not edit the following line - required for mem load use)
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// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m
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// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
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00000000
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// memory data file (do not edit the following line - required for mem load use)
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// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m
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// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
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00000000
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00000000
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114
control_unit.v
114
control_unit.v
@ -18,6 +18,40 @@
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// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
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// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
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//------------------------------------------------------------------------------------------
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//------------------------------------------------------------------------------------------
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`include "prj_definition.v"
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`include "prj_definition.v"
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`define ALU_ADD 6'h01
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`define ALU_SUB 6'h02
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`define ALU_MUL 6'h03
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`define ALU_SRL 6'h04
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`define ALU_SLL 6'h05
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`define ALU_AND 6'h06
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`define ALU_OR 6'h07
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`define ALU_NOR 6'h08
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`define ALU_SLT 6'h09
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`define OP_RTYPE 6'h00
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`define FN_ADD 6'h20
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`define FN_SUB 6'h22
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`define FN_MUL 6'h2c
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`define FN_AND 6'h24
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`define FN_OR 6'h25
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`define FN_NOR 6'h27
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`define FN_SLT 6'h2a
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`define FN_SLL 6'h01
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`define FN_SRL 6'h02
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`define FN_JR 6'h08
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`define OP_ADDI 6'h08
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`define OP_MULI 6'h1d
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`define OP_ANDI 6'h0c
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`define OP_ORI 6'h0d
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`define OP_LUI 6'h0f
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`define OP_SLTI 6'h0a
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`define OP_BEQ 6'h04
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`define OP_BNE 6'h05
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`define OP_LW 6'h23
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`define OP_SW 6'h2b
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module CONTROL_UNIT(CTRL, READ, WRITE, ZERO, INSTRUCTION, CLK, RST);
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module CONTROL_UNIT(CTRL, READ, WRITE, ZERO, INSTRUCTION, CLK, RST);
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// Output signals
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// Output signals
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output [`CTRL_WIDTH_INDEX_LIMIT:0] CTRL;
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output [`CTRL_WIDTH_INDEX_LIMIT:0] CTRL;
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@ -143,29 +177,15 @@ buf (CTRL[26], wa_sel_1);
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buf (CTRL[27], wa_sel_2);
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buf (CTRL[27], wa_sel_2);
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buf (CTRL[28], wa_sel_3);
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buf (CTRL[28], wa_sel_3);
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// Parse the instruction data, same as in data_path.v
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// Parse the instruction data
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wire [5:0] opcode;
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reg [5:0] opcode;
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wire [4:0] rs;
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reg [4:0] rs;
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wire [4:0] rt;
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reg [4:0] rt;
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wire [4:0] rd;
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reg [4:0] rd;
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wire [4:0] shamt;
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reg [4:0] shamt;
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wire [5:0] funct;
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reg [5:0] funct;
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wire [15:0] imm;
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reg [15:0] imm;
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wire [25:0] addr;
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reg [25:0] addr;
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// common for all
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buf opcode_buf [5:0] (opcode, INSTRUCTION[31:26]);
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// common for R-type, I-type
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buf rs_buf [4:0] (rs, INSTRUCTION[25:21]);
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buf rt_buf [4:0] (rt, INSTRUCTION[20:16]);
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// for R-type
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buf rd_buf [4:0] (rd, INSTRUCTION[15:11]);
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buf shamt_buf [4:0] (shamt, INSTRUCTION[10:6]);
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buf funct_buf [5:0] (funct, INSTRUCTION[5:0]);
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// for I-type
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buf imm_buf [15:0] (imm, INSTRUCTION[15:0]);
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// for J-type
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buf addr_buf [25:0] (addr, INSTRUCTION[25:0]);
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// State machine
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// State machine
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wire [2:0] state;
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wire [2:0] state;
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@ -173,6 +193,13 @@ PROC_SM proc_sm(state, CLK, RST);
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// TBD - take action on each +ve edge of clock
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// TBD - take action on each +ve edge of clock
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always @ (state) begin
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always @ (state) begin
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// R-type
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{opcode, rs, rt, rd, shamt, funct} = INSTRUCTION;
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// I-type
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{opcode, rs, rt, imm} = INSTRUCTION;
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// J-type
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{opcode, addr} = INSTRUCTION;
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// Print current state
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// Print current state
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$write("@ %6dns -> ", $time);
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$write("@ %6dns -> ", $time);
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$write("STATE ", state, ": ");
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$write("STATE ", state, ": ");
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@ -184,6 +211,7 @@ always @ (state) begin
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`PROC_WB: $write("WRITE BACK");
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`PROC_WB: $write("WRITE BACK");
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default: $write("INVALID");
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default: $write("INVALID");
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endcase
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endcase
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$write("\n");
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case (state)
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case (state)
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// fetch - next instruction from memory at PC
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// fetch - next instruction from memory at PC
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@ -230,15 +258,15 @@ always @ (state) begin
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// R-type
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// R-type
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if (opcode == 6'h00) begin
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if (opcode == 6'h00) begin
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case (funct)
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case (funct)
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6'h20: alu_oprn = 6'h01; // add
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6'h20: alu_oprn = `ALU_ADD;
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6'h22: alu_oprn = 6'h02; // sub
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6'h22: alu_oprn = `ALU_SUB;
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6'h2c: alu_oprn = 6'h03; // mul
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6'h2c: alu_oprn = `ALU_MUL;
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6'h02: alu_oprn = 6'h04; // srl
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6'h02: alu_oprn = `ALU_SRL;
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6'h01: alu_oprn = 6'h05; // sll
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6'h01: alu_oprn = `ALU_SLL;
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6'h24: alu_oprn = 6'h06; // and
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6'h24: alu_oprn = `ALU_AND;
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6'h25: alu_oprn = 6'h07; // or
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6'h25: alu_oprn = `ALU_OR;
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6'h27: alu_oprn = 6'h08; // nor
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6'h27: alu_oprn = `ALU_NOR;
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6'h2a: alu_oprn = 6'h09; // slt
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6'h2a: alu_oprn = `ALU_SLT;
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default: alu_oprn = 6'hxx;
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default: alu_oprn = 6'hxx;
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endcase
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endcase
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end
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end
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@ -246,18 +274,18 @@ always @ (state) begin
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else begin
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else begin
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case (opcode)
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case (opcode)
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// I-type
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// I-type
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6'h08: alu_oprn = 6'h01; // addi
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6'h08: alu_oprn = `ALU_ADD; // addi
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6'h1d: alu_oprn = 6'h03; // muli
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6'h1d: alu_oprn = `ALU_MUL; // muli
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6'h0c: alu_oprn = 6'h06; // andi
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6'h0c: alu_oprn = `ALU_AND; // andi
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6'h0d: alu_oprn = 6'h07; // ori
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6'h0d: alu_oprn = `ALU_OR; // ori
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6'h0a: alu_oprn = 6'h09; // slti
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6'h0a: alu_oprn = `ALU_SLT; // slti
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6'h04: alu_oprn = 6'h02; // beq - sub
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6'h04: alu_oprn = `ALU_SUB; // beq - sub
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6'h05: alu_oprn = 6'h02; // bne - sub
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6'h05: alu_oprn = `ALU_SUB; // bne - sub
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6'h23: alu_oprn = 6'h01; // lw - add
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6'h23: alu_oprn = `ALU_ADD; // lw - add
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6'h2b: alu_oprn = 6'h01; // sw - add
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6'h2b: alu_oprn = `ALU_ADD; // sw - add
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// J-type
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// J-type
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6'h1b: alu_oprn = 6'h02; // push - sub
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6'h1b: alu_oprn = `ALU_SUB; // push - sub
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6'h1c: alu_oprn = 6'h01; // pop - add
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6'h1c: alu_oprn = `ALU_ADD; // pop - add
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default: alu_oprn = 6'hxx;
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default: alu_oprn = 6'hxx;
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endcase
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endcase
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end
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end
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