diff --git a/.gitignore b/.gitignore index 92f4c49..231faec 100644 --- a/.gitignore +++ b/.gitignore @@ -27,3 +27,7 @@ sc_dpiheader.h vsim.dbg # End of https://www.toptal.com/developers/gitignore/api/modelsim + +!TESTPROGRAM/*.dat +!GOLDEN/*.dat +!OUTPUT/*.dat diff --git a/GOLDEN/CS147_FL15_HW01_02_mem_dump_golden.dat b/GOLDEN/CS147_FL15_HW01_02_mem_dump_golden.dat new file mode 100644 index 0000000..57d284a --- /dev/null +++ b/GOLDEN/CS147_FL15_HW01_02_mem_dump_golden.dat @@ -0,0 +1,13 @@ +// memory data file (do not edit the following line - required for mem load use) +// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/sram_32x64m +// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress +00000020 +00000020 +00000010 +00000010 +00000009 +00000008 +00000008 +00000005 +00000004 +00000002 diff --git a/GOLDEN/CS147_SP15_HW01_02_mem_dump_01_golden.dat b/GOLDEN/CS147_SP15_HW01_02_mem_dump_01_golden.dat new file mode 100644 index 0000000..3c8b717 --- /dev/null +++ b/GOLDEN/CS147_SP15_HW01_02_mem_dump_01_golden.dat @@ -0,0 +1,9 @@ +// memory data file (do not edit the following line - required for mem load use) +// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/sram_32x64m +// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress +00000001 +00000004 +00000004 +00000010 +00000010 +00000000 diff --git a/GOLDEN/CS147_SP15_HW01_02_mem_dump_02_golden.dat b/GOLDEN/CS147_SP15_HW01_02_mem_dump_02_golden.dat new file mode 100644 index 0000000..254ddab --- /dev/null +++ b/GOLDEN/CS147_SP15_HW01_02_mem_dump_02_golden.dat @@ -0,0 +1,9 @@ +// memory data file (do not edit the following line - required for mem load use) +// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/sram_32x64m +// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress +00000000 +00000020 +00000008 +00000008 +00000002 +00000002 diff --git a/GOLDEN/CS147_SP17_HW01_02_mem_dump_golden.dat b/GOLDEN/CS147_SP17_HW01_02_mem_dump_golden.dat new file mode 100644 index 0000000..fe7d590 --- /dev/null +++ b/GOLDEN/CS147_SP17_HW01_02_mem_dump_golden.dat @@ -0,0 +1,14 @@ +// memory data file (do not edit the following line - required for mem load use) +// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/sram_32x64m +// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress +00000015 +00000017 +00000019 +0000001b +0000001d +0000001f +00000021 +00000023 +00000025 +00000025 +00000000 diff --git a/GOLDEN/RevFib_mem_dump.golden.dat b/GOLDEN/RevFib_mem_dump.golden.dat new file mode 100644 index 0000000..19b3b06 --- /dev/null +++ b/GOLDEN/RevFib_mem_dump.golden.dat @@ -0,0 +1,19 @@ +// memory data file (do not edit the following line - required for mem load use) +// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/sram_32x64m +// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress +ffffffc9 +00000022 +ffffffeb +0000000d +fffffff8 +00000005 +fffffffd +00000002 +ffffffff +00000001 +00000000 +00000001 +00000001 +00000002 +00000003 +00000005 diff --git a/GOLDEN/fibonacci_mem_dump.golden.dat b/GOLDEN/fibonacci_mem_dump.golden.dat new file mode 100644 index 0000000..2c44fe1 --- /dev/null +++ b/GOLDEN/fibonacci_mem_dump.golden.dat @@ -0,0 +1,19 @@ +// memory data file (do not edit the following line - required for mem load use) +// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/sram_32x64m +// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress +00000000 +00000001 +00000001 +00000002 +00000003 +00000005 +00000008 +0000000d +00000015 +00000022 +00000037 +00000059 +00000090 +000000e9 +00000179 +00000262 diff --git a/OUTPUT/AND32_2x1_TB.out b/OUTPUT/AND32_2x1_TB.out new file mode 100755 index 0000000..dcf7ea5 --- /dev/null +++ b/OUTPUT/AND32_2x1_TB.out @@ -0,0 +1,8 @@ +// memory data file (do not edit the following line - required for mem load use) +// instance=/AND32_2x1_TB/result +// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress +00000000 +00000000 +00000000 +ffff0000 +0000ffff diff --git a/OUTPUT/CS147_FL15_HW01_02_mem_dump.dat b/OUTPUT/CS147_FL15_HW01_02_mem_dump.dat new file mode 100644 index 0000000..f6f6496 --- /dev/null +++ b/OUTPUT/CS147_FL15_HW01_02_mem_dump.dat @@ -0,0 +1,13 @@ +// memory data file (do not edit the following line - required for mem load use) +// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m +// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress +00000020 +00000020 +00000010 +00000010 +00000009 +00000008 +00000008 +00000005 +00000004 +00000002 diff --git a/OUTPUT/CS147_SP15_HW01_02_mem_dump_01.dat b/OUTPUT/CS147_SP15_HW01_02_mem_dump_01.dat new file mode 100644 index 0000000..25e4ab7 --- /dev/null +++ b/OUTPUT/CS147_SP15_HW01_02_mem_dump_01.dat @@ -0,0 +1,9 @@ +// memory data file (do not edit the following line - required for mem load use) +// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m +// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress +00000001 +00000004 +00000004 +00000010 +00000010 +00000000 diff --git a/OUTPUT/CS147_SP15_HW01_02_mem_dump_02.dat b/OUTPUT/CS147_SP15_HW01_02_mem_dump_02.dat new file mode 100644 index 0000000..62a9cae --- /dev/null +++ b/OUTPUT/CS147_SP15_HW01_02_mem_dump_02.dat @@ -0,0 +1,9 @@ +// memory data file (do not edit the following line - required for mem load use) +// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m +// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress +00000000 +00000020 +00000008 +00000008 +00000002 +00000002 diff --git a/OUTPUT/CS147_SP17_HW01_02_mem_dump.dat b/OUTPUT/CS147_SP17_HW01_02_mem_dump.dat new file mode 100644 index 0000000..99ec22b --- /dev/null +++ b/OUTPUT/CS147_SP17_HW01_02_mem_dump.dat @@ -0,0 +1,14 @@ +// memory data file (do not edit the following line - required for mem load use) +// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m +// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress +00000015 +00000017 +00000019 +0000001b +0000001d +0000001f +00000021 +00000023 +00000025 +00000025 +00000000 diff --git a/OUTPUT/INV32_1x1_TB.out b/OUTPUT/INV32_1x1_TB.out new file mode 100755 index 0000000..776b89d --- /dev/null +++ b/OUTPUT/INV32_1x1_TB.out @@ -0,0 +1,8 @@ +// memory data file (do not edit the following line - required for mem load use) +// instance=/INV32_1x1_TB/result +// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress +0000ffff +ffffffff +5a5a5a5a +0000ffff +ffff0000 diff --git a/OUTPUT/NOR32_2x1_TB.out b/OUTPUT/NOR32_2x1_TB.out new file mode 100755 index 0000000..a7f6b39 --- /dev/null +++ b/OUTPUT/NOR32_2x1_TB.out @@ -0,0 +1,8 @@ +// memory data file (do not edit the following line - required for mem load use) +// instance=/NOR32_2x1_TB/result +// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress +00000000 +ffffffff +00000000 +0000ffff +ffff0000 diff --git a/OUTPUT/OR32_2x1_TB.out b/OUTPUT/OR32_2x1_TB.out new file mode 100755 index 0000000..50bd555 --- /dev/null +++ b/OUTPUT/OR32_2x1_TB.out @@ -0,0 +1,8 @@ +// memory data file (do not edit the following line - required for mem load use) +// instance=/OR32_2x1_TB/result +// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress +ffffffff +00000000 +ffffffff +ffff0000 +0000ffff diff --git a/OUTPUT/RevFib_mem_dump.dat b/OUTPUT/RevFib_mem_dump.dat new file mode 100644 index 0000000..23be7b1 --- /dev/null +++ b/OUTPUT/RevFib_mem_dump.dat @@ -0,0 +1,19 @@ +// memory data file (do not edit the following line - required for mem load use) +// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m +// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress +ffffffc9 +00000022 +ffffffeb +0000000d +fffffff8 +00000005 +fffffffd +00000002 +ffffffff +00000001 +00000000 +00000001 +00000001 +00000002 +00000003 +00000005 diff --git a/OUTPUT/all_test_mem_dump_01.dat b/OUTPUT/all_test_mem_dump_01.dat new file mode 100644 index 0000000..20b6c36 --- /dev/null +++ b/OUTPUT/all_test_mem_dump_01.dat @@ -0,0 +1,21 @@ +// memory data file (do not edit the following line - required for mem load use) +// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m +// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress +00001337 +000039a5 +00002024 +0000335b +fffff313 +00000ced +026993bc +00000024 +00003337 +ffffccc8 +00000001 +00000000 +00013370 +00000133 +000039a5 +00000005 +00000005 +fffff313 diff --git a/OUTPUT/all_test_mem_dump_02.dat b/OUTPUT/all_test_mem_dump_02.dat new file mode 100644 index 0000000..d823fc2 --- /dev/null +++ b/OUTPUT/all_test_mem_dump_02.dat @@ -0,0 +1,9 @@ +// memory data file (do not edit the following line - required for mem load use) +// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m +// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress +00000000 +00000000 +00000000 +00000000 +00000000 +00001337 diff --git a/OUTPUT/alu_tb.out b/OUTPUT/alu_tb.out new file mode 100644 index 0000000..1743837 --- /dev/null +++ b/OUTPUT/alu_tb.out @@ -0,0 +1,147 @@ +// memory data file (do not edit the following line - required for mem load use) +// instance=/ALU_TB/result +// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress +00000014 +00000001 +00000000 +00000001 +00000064 +00000001 +00000000 +00000001 +00002800 +00000001 +0000000a +00000001 +0000000a +00000001 +fffffff5 +00000000 +00000000 +00000001 +00000000 +00000001 +ffffffe2 +00000001 +ffffff1f +00000000 +0001ffff +00000000 +fff88000 +00000001 +00000001 +00000000 +ffffffff +00000000 +00000000 +00000001 +00000001 +00000000 +00000000 +00000001 +00000032 +00000001 +fffffd8f +00000000 +00000000 +00000001 +00000000 +00000001 +00000001 +00000000 +ffffffff +00000000 +00000000 +00000001 +00000000 +00000001 +ffffffc4 +00000001 +00000000 +00000001 +00000384 +00000001 +00000000 +00000001 +00000000 +00000001 +ffffffe2 +00000001 +ffffffe2 +00000001 +0000001d +00000000 +00000000 +00000001 +00000000 +00000001 +00000000 +00000001 +00000000 +00000001 +00000000 +00000001 +00000000 +00000001 +00000000 +00000001 +00000000 +00000001 +ffffffff +00000000 +00000000 +00000001 +0000001b +00000000 +ffffffc7 +00000000 +fffffd8a +00000001 +00000000 +00000001 +00000000 +00000001 +00000020 +00000001 +fffffffb +00000000 +00000004 +00000001 +00000001 +00000000 +00000017 +00000000 +00000017 +00000000 +00000000 +00000001 +00000017 +00000000 +00000017 +00000000 +00000000 +00000001 +00000017 +00000000 +ffffffe8 +00000001 +00000000 +00000001 +00000046 +00000001 +ffffffba +00000001 +00000000 +00000001 +00000000 +00000001 +00000000 +00000001 +00000000 +00000001 +00000046 +00000001 +ffffffb9 +00000000 +00000001 +00000000 diff --git a/OUTPUT/barret_shifter_tb.out b/OUTPUT/barret_shifter_tb.out new file mode 100644 index 0000000..b637103 --- /dev/null +++ b/OUTPUT/barret_shifter_tb.out @@ -0,0 +1,129 @@ +// memory data file (do not edit the following line - required for mem load use) +// instance=/BARREL_SHIFTER32_TB/result +// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress +4b4b4b4a +96969694 +2d2d2d28 +5a5a5a50 +b4b4b4a0 +69696940 +d2d2d280 +a5a5a500 +4b4b4a00 +96969400 +2d2d2800 +5a5a5000 +b4b4a000 +69694000 +d2d28000 +a5a50000 +4b4a0000 +96940000 +2d280000 +5a500000 +b4a00000 +69400000 +d2800000 +a5000000 +4a000000 +94000000 +28000000 +50000000 +a0000000 +40000000 +80000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +52d2d2d2 +29696969 +14b4b4b4 +0a5a5a5a +052d2d2d +02969696 +014b4b4b +00a5a5a5 +0052d2d2 +00296969 +0014b4b4 +000a5a5a +00052d2d +00029696 +00014b4b +0000a5a5 +000052d2 +00002969 +000014b4 +00000a5a +0000052d +00000296 +0000014b +000000a5 +00000052 +00000029 +00000014 +0000000a +00000005 +00000002 +00000001 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +xxxxxxxx +xxxxxxxx diff --git a/OUTPUT/d_ff_tb.out b/OUTPUT/d_ff_tb.out new file mode 100644 index 0000000..74f90af --- /dev/null +++ b/OUTPUT/d_ff_tb.out @@ -0,0 +1,10 @@ +// memory data file (do not edit the following line - required for mem load use) +// instance=/D_FF_TB/result +// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress +00000012 +00000013 +0000000b +00000017 +0000000d +0000000f +00000017 diff --git a/OUTPUT/d_latch_tb.out b/OUTPUT/d_latch_tb.out new file mode 100644 index 0000000..2ba4e87 --- /dev/null +++ b/OUTPUT/d_latch_tb.out @@ -0,0 +1,11 @@ +// memory data file (do not edit the following line - required for mem load use) +// instance=/D_LATCH_TB/result +// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress +00000022 +00000023 +00000027 +00000011 +00000013 +00000017 +0000002f +0000001b diff --git a/OUTPUT/d_reg1_tb.out b/OUTPUT/d_reg1_tb.out new file mode 100644 index 0000000..7a825ba --- /dev/null +++ b/OUTPUT/d_reg1_tb.out @@ -0,0 +1,10 @@ +// memory data file (do not edit the following line - required for mem load use) +// instance=/REG1_TB/result +// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress +00000022 +00000023 +0000000b +0000002f +0000001d +0000001f +00000023 diff --git a/OUTPUT/d_reg32_tb.out b/OUTPUT/d_reg32_tb.out new file mode 100644 index 0000000..85f380e --- /dev/null +++ b/OUTPUT/d_reg32_tb.out @@ -0,0 +1,11 @@ +// memory data file (do not edit the following line - required for mem load use) +// instance=/REG32_TB/result +// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress +00000000 +00000000 +a5a5a5a5 +ffff0000 +00000000 +00000000 +0000ffff +0000ffff diff --git a/OUTPUT/decoder_5x32_tb.out b/OUTPUT/decoder_5x32_tb.out new file mode 100644 index 0000000..b944b99 --- /dev/null +++ b/OUTPUT/decoder_5x32_tb.out @@ -0,0 +1,35 @@ +// memory data file (do not edit the following line - required for mem load use) +// instance=/DECODER_5x32_TB/result +// format=bin addressradix=h dataradix=b version=1.0 wordsperline=1 noaddress +00000000000000000000000000000001 +00000000000000000000000000000010 +00000000000000000000000000000100 +00000000000000000000000000001000 +00000000000000000000000000010000 +00000000000000000000000000100000 +00000000000000000000000001000000 +00000000000000000000000010000000 +00000000000000000000000100000000 +00000000000000000000001000000000 +00000000000000000000010000000000 +00000000000000000000100000000000 +00000000000000000001000000000000 +00000000000000000010000000000000 +00000000000000000100000000000000 +00000000000000001000000000000000 +00000000000000010000000000000000 +00000000000000100000000000000000 +00000000000001000000000000000000 +00000000000010000000000000000000 +00000000000100000000000000000000 +00000000001000000000000000000000 +00000000010000000000000000000000 +00000000100000000000000000000000 +00000001000000000000000000000000 +00000010000000000000000000000000 +00000100000000000000000000000000 +00001000000000000000000000000000 +00010000000000000000000000000000 +00100000000000000000000000000000 +01000000000000000000000000000000 +10000000000000000000000000000000 diff --git a/OUTPUT/fibonacci_mem_dump.dat b/OUTPUT/fibonacci_mem_dump.dat new file mode 100644 index 0000000..8f7ed59 --- /dev/null +++ b/OUTPUT/fibonacci_mem_dump.dat @@ -0,0 +1,19 @@ +// memory data file (do not edit the following line - required for mem load use) +// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m +// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress +00000000 +00000001 +00000001 +00000002 +00000003 +00000005 +00000008 +0000000d +00000015 +00000022 +00000037 +00000059 +00000090 +000000e9 +00000179 +00000262 diff --git a/OUTPUT/full_adder.out b/OUTPUT/full_adder.out new file mode 100644 index 0000000..6c019d4 --- /dev/null +++ b/OUTPUT/full_adder.out @@ -0,0 +1,11 @@ +// memory data file (do not edit the following line - required for mem load use) +// instance=/FULL_ADDER_TB/result +// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress +00000000 +00000001 +00000001 +00000002 +00000001 +00000002 +00000002 +00000003 diff --git a/OUTPUT/half_adder.out b/OUTPUT/half_adder.out new file mode 100644 index 0000000..7649f00 --- /dev/null +++ b/OUTPUT/half_adder.out @@ -0,0 +1,7 @@ +// memory data file (do not edit the following line - required for mem load use) +// instance=/HALF_ADDER_TB/results +// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress +00000000 +00000001 +00000001 +00000002 diff --git a/OUTPUT/mult32_tb.out b/OUTPUT/mult32_tb.out new file mode 100644 index 0000000..510e496 --- /dev/null +++ b/OUTPUT/mult32_tb.out @@ -0,0 +1,11 @@ +// memory data file (do not edit the following line - required for mem load use) +// instance=/MULT_TB/result +// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress +00000000000000c8 +000000000000002d +ffffffffffffff90 +ffffffffffffff42 +3100000000000000 +cf00000000000000 +cf00000000000000 +3100000000000000 diff --git a/OUTPUT/mult32_u_tb.out b/OUTPUT/mult32_u_tb.out new file mode 100644 index 0000000..20b79ab --- /dev/null +++ b/OUTPUT/mult32_u_tb.out @@ -0,0 +1,8 @@ +// memory data file (do not edit the following line - required for mem load use) +// instance=/MULT_U_TB/result +// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress +00000000000000c8 +000000000000002d +0000000000000070 +00000000000000be +006975a0b62bf524 diff --git a/OUTPUT/mux32_16x1_tb.out b/OUTPUT/mux32_16x1_tb.out new file mode 100644 index 0000000..3c916bd --- /dev/null +++ b/OUTPUT/mux32_16x1_tb.out @@ -0,0 +1,19 @@ +// memory data file (do not edit the following line - required for mem load use) +// instance=/MUX32_16x1_TB/result +// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress +00000000 +00000001 +00000002 +00000003 +00000004 +00000005 +00000006 +00000007 +00000008 +00000009 +0000000a +0000000b +0000000c +0000000d +0000000e +0000000f diff --git a/OUTPUT/mux32_2x1_tb.out b/OUTPUT/mux32_2x1_tb.out new file mode 100644 index 0000000..e39c575 --- /dev/null +++ b/OUTPUT/mux32_2x1_tb.out @@ -0,0 +1,5 @@ +// memory data file (do not edit the following line - required for mem load use) +// instance=/MUX32_2x1_TB/result +// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress +a5a5a5a5 +5a5a5a5a diff --git a/OUTPUT/mux32_32x1_tb.out b/OUTPUT/mux32_32x1_tb.out new file mode 100644 index 0000000..a7a230c --- /dev/null +++ b/OUTPUT/mux32_32x1_tb.out @@ -0,0 +1,35 @@ +// memory data file (do not edit the following line - required for mem load use) +// instance=/MUX32_32x1_TB/result +// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress +00000000 +00000001 +00000002 +00000003 +00000004 +00000005 +00000006 +00000007 +00000008 +00000009 +0000000a +0000000b +0000000c +0000000d +0000000e +0000000f +00000010 +00000011 +00000012 +00000013 +00000014 +00000015 +00000016 +00000017 +00000018 +00000019 +0000001a +0000001b +0000001c +0000001d +0000001e +0000001f diff --git a/OUTPUT/rc_add_sub_32.out b/OUTPUT/rc_add_sub_32.out new file mode 100644 index 0000000..4a19897 --- /dev/null +++ b/OUTPUT/rc_add_sub_32.out @@ -0,0 +1,8 @@ +// memory data file (do not edit the following line - required for mem load use) +// instance=/RC_ADD_SUB_32_TB/result +// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress +0000001e +fffffff6 +00000003 +00000004 +00005555 diff --git a/OUTPUT/rf_tb.out b/OUTPUT/rf_tb.out new file mode 100644 index 0000000..26a2999 --- /dev/null +++ b/OUTPUT/rf_tb.out @@ -0,0 +1,67 @@ +// memory data file (do not edit the following line - required for mem load use) +// instance=/RF_TB/result +// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress +00000000 +0000000a +00000014 +0000001e +00000028 +00000032 +0000003c +00000046 +00000050 +0000005a +00000064 +0000006e +00000078 +00000082 +0000008c +00000096 +000000a0 +000000aa +000000b4 +000000be +000000c8 +000000d2 +000000dc +000000e6 +000000f0 +000000fa +00000104 +0000010e +00000118 +00000122 +0000012c +00000136 +00000014 +00000014 +00000014 +00000014 +00000014 +00000014 +00000014 +00000014 +00000014 +00000014 +00000014 +00000014 +00000014 +00000014 +xxxxxxxx +xxxxxxxx +xxxxxxxx +xxxxxxxx +xxxxxxxx +xxxxxxxx +xxxxxxxx +xxxxxxxx +xxxxxxxx +xxxxxxxx +xxxxxxxx +xxxxxxxx +xxxxxxxx +xxxxxxxx +xxxxxxxx +xxxxxxxx +xxxxxxxx +xxxxxxxx diff --git a/OUTPUT/sr_latch_tb.out b/OUTPUT/sr_latch_tb.out new file mode 100644 index 0000000..e0379d2 --- /dev/null +++ b/OUTPUT/sr_latch_tb.out @@ -0,0 +1,17 @@ +// memory data file (do not edit the following line - required for mem load use) +// instance=/SR_LATCH_TB/result +// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress +00000042 +00000043 +00000047 +0000004b +0000004f +00000021 +00000023 +00000027 +0000002b +0000002f +0000005b +00000053 +00000037 +00000033 diff --git a/OUTPUT/twoscomp32_tb.out b/OUTPUT/twoscomp32_tb.out new file mode 100644 index 0000000..5e28566 --- /dev/null +++ b/OUTPUT/twoscomp32_tb.out @@ -0,0 +1,5 @@ +// memory data file (do not edit the following line - required for mem load use) +// instance=/TWOSCOMP32_TB/result +// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress +fffffff6 +00000005 diff --git a/OUTPUT/twoscomp64_tb.out b/OUTPUT/twoscomp64_tb.out new file mode 100644 index 0000000..b344911 --- /dev/null +++ b/OUTPUT/twoscomp64_tb.out @@ -0,0 +1,5 @@ +// memory data file (do not edit the following line - required for mem load use) +// instance=/TWOSCOMP64_TB/result +// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress +fffffffffffffff6 +0000000000000005 diff --git a/TESTBENCH/da_vinci_tb.v b/TESTBENCH/da_vinci_tb.v index 49b534b..c89405f 100644 --- a/TESTBENCH/da_vinci_tb.v +++ b/TESTBENCH/da_vinci_tb.v @@ -30,7 +30,8 @@ wire [`DATA_INDEX_LIMIT:0] MEM_DATA_OUT, MEM_DATA_IN; // reset reg RST; -integer t1=1, t2=1, t3=1, t4=1, t5=1; +integer t1=1, t2=1, t3=1, t4=1, t5=1, t6=1; +//integer t1=0, t2=0, t3=0, t4=0, t5=0, t6=1; // Clock generator instance CLK_GENERATOR clk_gen_inst(.CLK(CLK)); @@ -62,7 +63,7 @@ begin #5000 $write("\n"); $write("===> Done simulating fibonacci.dat\n", ""); $write("\n"); - $writememh("./OUTPUT/fibonacci_mem_dump.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h01000000, 'h0100000f); + $writememh("./OUTPUT/fibonacci_mem_dump.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h00040000, 'h0004000f); /* END : test 1*/ end @@ -78,7 +79,7 @@ begin #5000 $write("\n"); $write("===> Done simulating RevFib.dat\n", ""); $write("\n"); - $writememh("./OUTPUT/RevFib_mem_dump.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h03fffff0, 'h03ffffff); + $writememh("./OUTPUT/RevFib_mem_dump.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, `INIT_STACK_POINTER - 'h0f, `INIT_STACK_POINTER); /* END : test 2*/ end @@ -94,7 +95,7 @@ begin #5000 $write("\n"); $write("===> Done simulating CS147_SP17_HW01_02.dat\n", ""); $write("\n"); - $writememh("./OUTPUT/CS147_SP17_HW01_02_mem_dump.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h01008000, 'h0100800A); + $writememh("./OUTPUT/CS147_SP17_HW01_02_mem_dump.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h00048000, 'h0004800A); /* END : test 3*/ end @@ -110,7 +111,7 @@ begin #6000 $write("\n"); $write("===> Done simulating CS147_FL15_HW01_02.dat\n", ""); $write("\n"); - $writememh("./OUTPUT/CS147_FL15_HW01_02_mem_dump.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h03fffff6, 'h03ffffff); + $writememh("./OUTPUT/CS147_FL15_HW01_02_mem_dump.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, `INIT_STACK_POINTER - 9, `INIT_STACK_POINTER); /* END : test 4*/ end @@ -126,9 +127,26 @@ begin #5000 $write("\n"); $write("===> Done simulating CS147_SP15_HW01_02.dat\n", ""); $write("\n"); - $writememh("./OUTPUT/CS147_SP15_HW01_02_mem_dump_01.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h01008000, 'h01008005); - $writememh("./OUTPUT/CS147_SP15_HW01_02_mem_dump_02.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h03fffffA, 'h03ffffff); + $writememh("./OUTPUT/CS147_SP15_HW01_02_mem_dump_01.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h00048000, 'h00048005); + $writememh("./OUTPUT/CS147_SP15_HW01_02_mem_dump_02.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, `INIT_STACK_POINTER - 5, `INIT_STACK_POINTER); /* END : test 5*/ +end + +if (t6 === 1) +begin +/* START : test 6*/ +#5 RST=1'b0; +#5 RST=1'b1; + $write("\n"); + $write("===> Simulating all_test.dat\n", ""); + $write("\n"); + $readmemh("./TESTPROGRAM/all_test.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m); +#5000 $write("\n"); + $write("===> Done simulating all_test.dat\n", ""); + $write("\n"); + $writememh("./OUTPUT/all_test_mem_dump_01.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h00048000, 'h00048011); + $writememh("./OUTPUT/all_test_mem_dump_02.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, `INIT_STACK_POINTER - 5, `INIT_STACK_POINTER); +/* END : test 6*/ end $stop; diff --git a/TESTPROGRAM/CS147_FL15_HW01_02.dat b/TESTPROGRAM/CS147_FL15_HW01_02.dat new file mode 100644 index 0000000..3028352 --- /dev/null +++ b/TESTPROGRAM/CS147_FL15_HW01_02.dat @@ -0,0 +1,45 @@ +// ------ Program Part ---- +@0001000 +2021000A // addi r1, r1, 0xA; +20420048 // addi r2, r2, 0x0048; +00401301 // sll r2, r2, 0xC; +00411820 // add r3, r2, r1; +3C848000 // lui r4, r4, 0x8000; +8C450000 // LOOP: lw r5, r2,0x0; +8C660000 // lw r6, r3, 0x0; +00A63822 // sub r7, r5, r6; +00E44024 // and r8, r7, r4; +15280003 // bne r8, r9, L1; +20C00000 // addi r0, r6, 0x0; +20630001 // addi r3, r3, 0x1; +0800100F // jmp L2; +20A00000 // L1: addi r0, r5, 0x0; +20420001 // addi r2, r2, 0x1; +6C000000 // L2: push +2021FFFF // addi r1, r1, 0xFFFF; +1521FFF3 // bne r1, r9, LOOP; + + +// ------ Data Part ---- +@00048000 +005 // 0004 8000 +008 // 0004 8001 +009 // 0004 8002 +010 // 0004 8003 +020 // 0004 8004 +029 // 0004 8005 +02D // 0004 8006 +02F // 0004 8007 +032 // 0004 8008 +037 // 0004 8009 +002 // 0004 800A +004 // 0004 800B +008 // 0004 800C +010 // 0004 800D +020 // 0004 800E +040 // 0004 800F +080 // 0004 8010 +100 // 0004 8011 +200 // 0004 8012 +400 // 0004 8013 + diff --git a/TESTPROGRAM/CS147_SP15_HW01_02.dat b/TESTPROGRAM/CS147_SP15_HW01_02.dat new file mode 100644 index 0000000..052aeb0 --- /dev/null +++ b/TESTPROGRAM/CS147_SP15_HW01_02.dat @@ -0,0 +1,21 @@ +@0001000 +20000001 // addi r0, r0, 0x1; +20210002 // addi r1, r1, 0x2; +20420000 // addi r2, r2, 0x0; +3C630004 // lui r3, 0x0004; +34638000 // ori r3, r3, 0x8000; +20840005 // addi r4, r4, 0x5; +00010020 // LOOP: add r0, r0, r1; +00010822 // sub r1, r0, r1; +00010022 // sub r0, r0, r1; +AC610000 // sw r1, r3, 0x0; +20630001 // addi r3, r3, 0x1; +6C000000 // push; +00000041 // sll r0, r0, 0x1; +00200841 // sll r1, r1, 0x1; +20420001 // addi r2, r2, 0x1; +1482FFF6 // bne r2, r4, LOOP; + + + + diff --git a/TESTPROGRAM/CS147_SP17_HW01_02.dat b/TESTPROGRAM/CS147_SP17_HW01_02.dat new file mode 100644 index 0000000..602d586 --- /dev/null +++ b/TESTPROGRAM/CS147_SP17_HW01_02.dat @@ -0,0 +1,28 @@ +// ------ Program Part ---- +@0001000 +20000048 // addi r0, r0, 0x0048 +00000301 // sll r0, r0, 0xC +20420009 // addi r2, r2, 0x9 +10410007 // LOOP: beq r1, r2, END +8C030000 // lw r3, r0, 0x0 +8C040001 // lw r4, r0, 0x1 +00642820 // add r5, r3, r4 +AC050000 // sw r5, r0, 0x0 +20000001 // addi r0, r0, 0x1 +20210001 // addi r1, r1, 0x1 +08001003 // j LOOP +AC050000 // END: sw r5, r0, 0x0 + +// ------ Data Part ---- +@00048000 +0A // 0004 8000 +0B // 0004 8001 +0C // 0004 8002 +0D // 0004 8003 +0E // 0004 8004 +0F // 0004 8005 +10 // 0004 8006 +11 // 0004 8007 +12 // 0004 8008 +13 // 0004 8008 + diff --git a/TESTPROGRAM/RevFib.dat b/TESTPROGRAM/RevFib.dat new file mode 100644 index 0000000..9d52b1e --- /dev/null +++ b/TESTPROGRAM/RevFib.dat @@ -0,0 +1,16 @@ +@0001000 +20210005 // addi r1, r1, 0x5 +20420003 // addi r2, r2, 0x3 +20200000 // addi r0, r1, 0x0 +6c000000 // push +20400000 // loop : addi r0, r2, 0x0 +6c000000 // push +20430000 // addi r3, r2, 0x0 +00221022 // sub r2, r1, r2 +20610000 // addi r1, r3, 0x0 +08001004 // jmp loop +00000000 // nop +00000000 // nop + + + diff --git a/TESTPROGRAM/all_test.dat b/TESTPROGRAM/all_test.dat new file mode 100644 index 0000000..7493e86 --- /dev/null +++ b/TESTPROGRAM/all_test.dat @@ -0,0 +1,49 @@ +@0001000 +20001337 // addi r0, r0, 0x1337 +6c000000 // push +3c1e0004 // lui r30, 0x0004 +37de8000 // ori r30, r30 0x00008000 +afc00000 // sw r0, r30, 0x0 +0c001014 // jal 0x00001014 +70000000 // pop +20212024 // addi r1, r1, 0x2024 +00011020 // add r2, r0, r1 +00011822 // sub r3, r0, r1 +00202022 // sub r4, r1, r0 +0001282c // mul r5, r0, r1 +00013024 // and r6, r0, r1 +00013825 // or r7, r0, r1 +00014027 // nor r8, r0, r1 +0001482a // slt r9, r0, r1 +0020502a // slt r10, r1, r0 +00005901 // sll r11, r0, 4 +00006102 // srl r12, r0, 4 +08001017 // jmp 0x00001017 +74000003 // muli r0, r0, 3 +afc00001 // sw r0, r30, 0x1 +03e00008 // jr r31 +8fcd0001 // lw r13, r30, 0x1 +29ae1338 // slti r14, r13, 0x1338 +302f0000 // andi r15, r1, 0x0 +21ef0005 // addi r15, r15, 0x5 +11ee0002 // beq r14, r15, 0x2 +21ce0001 // addi r14, r14, 0x1 +0800101b // jmp 0x0000101b +afc10002 // sw r1, r30, 0x2 +afc20003 // sw r2, r30, 0x3 +afc30004 // sw r3, r30, 0x4 +afc40005 // sw r4, r30, 0x5 +afc50006 // sw r5, r30, 0x6 +afc60007 // sw r6, r30, 0x7 +afc70008 // sw r7, r30, 0x8 +afc80009 // sw r8, r30, 0x9 +afc9000a // sw r9, r30, 0x0a +afca000b // sw r10, r30, 0x0b +afcb000c // sw r11, r30, 0x0c +afcc000d // sw r12, r30, 0x0d +afcd000e // sw r13, r30, 0x0e +afce000f // sw r14, r30, 0x0f +afcf0010 // sw r15, r30, 0x10 +2210fbb1 // addi r16, r16, 0xfbb1 +1470fffe // bne r16, r3, 0xfffe +afd00011 // sw r16, r30, 0x11 diff --git a/TESTPROGRAM/fibonacci.dat b/TESTPROGRAM/fibonacci.dat new file mode 100644 index 0000000..79a12d4 --- /dev/null +++ b/TESTPROGRAM/fibonacci.dat @@ -0,0 +1,13 @@ +@0001000 +20420001 // addi r2, r2, 0x0001; +3C000004 // lui r0, 0x0004; +AC010000 // sw r1, r0, 0x0000; +20000001 // loop: addi r0, r0, 0x0001; +AC020000 // sw r2, r0, 0x0000; +20430000 // addi r3, r2, 0x0000; +00411020 // add r2, r2, r1; +20610000 // addi r1, r3, 0x0000; +08001003 // jmp loop; + + + diff --git a/TESTPROGRAM/mem_content_01.dat b/TESTPROGRAM/mem_content_01.dat new file mode 100644 index 0000000..c0460f4 --- /dev/null +++ b/TESTPROGRAM/mem_content_01.dat @@ -0,0 +1,11 @@ +@0001000 +00414020 00414021 00414022 00414023 // sample data +00414024 00414025 00414026 00414027 +00414028 00414029 0041402a 0041402b +0041402c 0041402d 0041402e 0041402f + +@002f00a +00514020 00514021 00514022 00514023 +00514024 00514025 00514026 00514027 +00514028 00514029 0051402a 0051402b +0051402c 0051402d 0051402e 0051402f \ No newline at end of file diff --git a/control_unit.v b/control_unit.v index b2bda1c..40fd783 100644 --- a/control_unit.v +++ b/control_unit.v @@ -18,7 +18,85 @@ // 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation //------------------------------------------------------------------------------------------ `include "prj_definition.v" -module CONTROL_UNIT(CTRL, READ, WRITE, ZERO, INSTRUCTION, CLK, RST); + +// Control signals, referenced in data_path.v +`define pc_load 0 +`define pc_sel_1 1 +`define pc_sel_2 2 +`define pc_sel_3 3 + +`define ir_load 4 + +`define r1_sel_1 5 +`define reg_r 6 +`define reg_w 7 + +`define sp_load 8 + +`define op1_sel_1 9 +`define op2_sel_1 10 +`define op2_sel_2 11 +`define op2_sel_3 12 +`define op2_sel_4 13 + +`define alu_oprn 19:14 + +`define ma_sel_1 20 +`define ma_sel_2 21 + +`define md_sel_1 22 + +`define wd_sel_1 23 +`define wd_sel_2 24 +`define wd_sel_3 25 + +`define wa_sel_1 26 +`define wa_sel_2 27 +`define wa_sel_3 28 + +// ALU operation codes +`define ALU_NOP 6'h00 +`define ALU_ADD 6'h01 +`define ALU_SUB 6'h02 +`define ALU_MUL 6'h03 +`define ALU_SRL 6'h04 +`define ALU_SLL 6'h05 +`define ALU_AND 6'h06 +`define ALU_OR 6'h07 +`define ALU_NOR 6'h08 +`define ALU_SLT 6'h09 + +// Instruction opcodes +// R-type +`define OP_RTYPE 6'h00 +`define FN_ADD 6'h20 +`define FN_SUB 6'h22 +`define FN_MUL 6'h2c +`define FN_AND 6'h24 +`define FN_OR 6'h25 +`define FN_NOR 6'h27 +`define FN_SLT 6'h2a +`define FN_SLL 6'h01 +`define FN_SRL 6'h02 +`define FN_JR 6'h08 +// I-type +`define OP_ADDI 6'h08 +`define OP_MULI 6'h1d +`define OP_ANDI 6'h0c +`define OP_ORI 6'h0d +`define OP_LUI 6'h0f +`define OP_SLTI 6'h0a +`define OP_BEQ 6'h04 +`define OP_BNE 6'h05 +`define OP_LW 6'h23 +`define OP_SW 6'h2b +// J-type +`define OP_JMP 6'h02 +`define OP_JAL 6'h03 +`define OP_PUSH 6'h1b +`define OP_POP 6'h1c + +module CONTROL_UNIT(CTRL, READ, WRITE, ZERO, INSTRUCTION, CLK, RST); // Output signals output [`CTRL_WIDTH_INDEX_LIMIT:0] CTRL; output READ, WRITE; @@ -26,22 +104,247 @@ output READ, WRITE; // input signals input ZERO, CLK, RST; input [`DATA_INDEX_LIMIT:0] INSTRUCTION; - -// TBD - take action on each +ve edge of clock +// Task to print instruction +task print_instruction; +input [`DATA_INDEX_LIMIT:0] inst; +reg [5:0] opcode; +reg [4:0] rs; +reg [4:0] rt; +reg [4:0] rd; +reg [4:0] shamt; +reg [5:0] funct; +reg [15:0] imm; +reg [25:0] addr; +begin +// parse the instruction +// R-type +{opcode, rs, rt, rd, shamt, funct} = inst; +// I-type +{opcode, rs, rt, imm} = inst; +// J-type +{opcode, addr} = inst; + +$write("@ %6dns -> [0X%08h] ", $time, inst); + +case(opcode) + // R-Type + `OP_RTYPE: case(funct) + `FN_ADD: $write("add r[%02d], r[%02d], r[%02d];", rd, rs, rt); + `FN_SUB: $write("sub r[%02d], r[%02d], r[%02d];", rd, rs, rt); + `FN_MUL: $write("mul r[%02d], r[%02d], r[%02d];", rd, rs, rt); + `FN_AND: $write("and r[%02d], r[%02d], r[%02d];", rd, rs, rt); + `FN_OR: $write("or r[%02d], r[%02d], r[%02d];", rd, rs, rt); + `FN_NOR: $write("nor r[%02d], r[%02d], r[%02d];", rd, rs, rt); + `FN_SLT: $write("slt r[%02d], r[%02d], r[%02d];", rd, rs, rt); + `FN_SLL: $write("sll r[%02d], r[%02d], %2d;", rd, rs, shamt); + `FN_SRL: $write("srl r[%02d], 0X%02h, r[%02d];", rd, rs, shamt); + `FN_JR: $write("jr r[%02d];", rs); + default: $write(""); + endcase + // I-type + `OP_ADDI: $write("addi r[%02d], r[%02d], 0X%04h;", rt, rs, imm); + `OP_MULI: $write("muli r[%02d], r[%02d], 0X%04h;", rt, rs, imm); + `OP_ANDI: $write("andi r[%02d], r[%02d], 0X%04h;", rt, rs, imm); + `OP_ORI: $write("ori r[%02d], r[%02d], 0X%04h;", rt, rs, imm); + `OP_LUI: $write("lui r[%02d], 0X%04h;", rt, imm); + `OP_SLTI: $write("slti r[%02d], r[%02d], 0X%04h;", rt, rs, imm); + `OP_BEQ: $write("beq r[%02d], r[%02d], 0X%04h;", rt, rs, imm); + `OP_BNE: $write("bne r[%02d], r[%02d], 0X%04h;", rt, rs, imm); + `OP_LW: $write("lw r[%02d], r[%02d], 0X%04h;", rt, rs, imm); + `OP_SW: $write("sw r[%02d], r[%02d], 0X%04h;", rt, rs, imm); + // J-Type + `OP_JMP: $write("jmp 0X%07h;", addr); + `OP_JAL: $write("jal 0X%07h;", addr); + `OP_PUSH: $write("push;"); + `OP_POP: $write("pop;"); + default: $write(""); +endcase + +$write("\n"); +end +endtask + +reg read, write; +buf (READ, read); +buf (WRITE, write); + +reg [31:0] C; + +buf ctrl_buf [31:0] (CTRL, C); + +// Parse the instruction data +reg [5:0] opcode; +reg [4:0] rs; +reg [4:0] rt; +reg [4:0] rd; +reg [4:0] shamt; +reg [5:0] funct; +reg [15:0] imm; +reg [25:0] addr; + +// State machine +wire [2:0] state; +PROC_SM proc_sm(state, CLK, RST); + +// take action on each +ve edge of clock +always @ (state) begin + // R-type + {opcode, rs, rt, rd, shamt, funct} = INSTRUCTION; + // I-type + {opcode, rs, rt, imm} = INSTRUCTION; + // J-type + {opcode, addr} = INSTRUCTION; + + case (state) + // fetch - next instruction from memory at PC + `PROC_FETCH: begin + // set everything in ctrl to 0 + C = 32'b0; + // memory + read = 1'b1; + write = 1'b0; + // ma_sel_2: load data from mem[PC] + C[`ma_sel_2] = 1'b1; + end + // decode - parse instruction and read values from register file + `PROC_DECODE: begin + // loaded in previous state, set to 0 + C[`ma_sel_2] = 1'b0; + read = 1'b0; + // load now + C[`ir_load] = 1'b1; + C[`reg_r] = 1'b1; + end + // execute - perform operation based on instruction + `PROC_EXE: begin + print_instruction(INSTRUCTION); + // loaded in previous state, set to 0 + C[`ir_load] = 1'b0; + // load now - sp is incremented before pop + C[`sp_load] = opcode == `OP_POP; + + // r1_sel_1: rs by default (0), push - r1 (1) + C[`r1_sel_1] = opcode == `OP_PUSH; + + // wa_sel_1: R-type - write to rd (0), I-type - write to rt (1) + C[`wa_sel_1] = opcode != `OP_RTYPE; + // wa_sel_2: pop - write to r0 (0), jal - write to r31 (1) + C[`wa_sel_2] = opcode == `OP_JAL; + // wa_sel_3: wa_sel_2 if push or pop or jal (0), else wa_sel_1 (1) + C[`wa_sel_3] = ~(opcode == `OP_PUSH || opcode == `OP_POP || opcode == `OP_JAL); + + // pc_sel_1: jr - jump to address in rs (0), else pc_inc (1) + C[`pc_sel_1] = ~(opcode == `OP_RTYPE && funct == `FN_JR); + // pc_sel_2: pc_sel_1 by default (0), beq, bne - branch if equal or not equal (1) + // pc_sel_2 is set after EXE because it depends on ZERO + // pc_sel_3: jmp or jal - jump to address (0), else pc_sel_2 (1) + C[`pc_sel_3] = ~(opcode == `OP_JMP || opcode == `OP_JAL); + + // alu_oprn - operation to be performed by ALU + case (opcode) + // R-type + `OP_RTYPE: case (funct) + `FN_ADD: C[`alu_oprn] = `ALU_ADD; + `FN_SUB: C[`alu_oprn] = `ALU_SUB; + `FN_MUL: C[`alu_oprn] = `ALU_MUL; + `FN_SRL: C[`alu_oprn] = `ALU_SRL; + `FN_SLL: C[`alu_oprn] = `ALU_SLL; + `FN_AND: C[`alu_oprn] = `ALU_AND; + `FN_OR: C[`alu_oprn] = `ALU_OR; + `FN_NOR: C[`alu_oprn] = `ALU_NOR; + `FN_SLT: C[`alu_oprn] = `ALU_SLT; + default: C[`alu_oprn] = `ALU_NOP; + endcase + // I-type + `OP_ADDI: C[`alu_oprn] = `ALU_ADD; // addi + `OP_MULI: C[`alu_oprn] = `ALU_MUL; // muli + `OP_ANDI: C[`alu_oprn] = `ALU_AND; // andi + `OP_ORI: C[`alu_oprn] = `ALU_OR; // ori + `OP_SLTI: C[`alu_oprn] = `ALU_SLT; // slti + `OP_BEQ: C[`alu_oprn] = `ALU_SUB; // beq - sub + `OP_BNE: C[`alu_oprn] = `ALU_SUB; // bne - sub + `OP_LW: C[`alu_oprn] = `ALU_ADD; // lw - add + `OP_SW: C[`alu_oprn] = `ALU_ADD; // sw - add + // J-type + `OP_PUSH: C[`alu_oprn] = `ALU_SUB; // push - sub + `OP_POP: C[`alu_oprn] = `ALU_ADD; // pop - add + default: C[`alu_oprn] = `ALU_NOP; + endcase + + // op1_sel_1: r1 by default (0), push or pop - sp (1) + C[`op1_sel_1] = opcode == `OP_PUSH || opcode == `OP_POP; + + // op2_sel_1: const 1 (for inc/dec) (0), shamt for sll/srl (1) + C[`op2_sel_1] = opcode == `OP_RTYPE && (funct == `FN_SLL || funct == `FN_SRL); + // op2_sel_2: imm_zx for logical and/or (0), imm_sx otherise (1) + // ('nor' not availble in I-type) + C[`op2_sel_2] = ~(opcode == `OP_ANDI || opcode == `OP_ORI); + // op2_sel_3: op2_sel_2 for I-type (0), op2_sel_1 for R-type shift or inc/dec (1) + // (inc/dec is for sp with pop or push) + C[`op2_sel_3] = opcode == `OP_RTYPE || opcode == `OP_PUSH || opcode == `OP_POP; + // op2_sel_4: op2_sel_3 for I-type (except beq, bne) or R-type shift or inc/dec (0), else r2 (1) + // i.e. r2 if R-type (except sll/srl), or bne/beq + C[`op2_sel_4] = opcode == `OP_RTYPE && ~(funct == `FN_SLL || funct == `FN_SRL) + || opcode == `OP_BEQ || opcode == `OP_BNE; + + // wd_sel_1: alu_out by default (0), DATA_IN for lw or pop (1) + C[`wd_sel_1] = opcode == `OP_LW || opcode == `OP_POP; + // wd_sel_2: wd_sel_1 by default (0), imm_zx_lsb for lui (1) + C[`wd_sel_2] = opcode == `OP_LUI; + // wd_sel_3: pc_inc for jal (0), else wd_sel_2 (1) + C[`wd_sel_3] = ~(opcode == `OP_JAL); + + // ma_sel_1: alu_out for lw or sw (0), sp for push or pop (1) + C[`ma_sel_1] = opcode == `OP_PUSH || opcode == `OP_POP; + // ma_sel_2: 0 for every memory access instruction (lw, sw, push, pop), 1 for fetch + C[`ma_sel_2] = 1'b0; + + // md_sel_1: r2 for sw (0), r1 for push (1) + C[`md_sel_1] = opcode == `OP_PUSH; + end + `PROC_MEM: begin + // loaded in previous state, set to 0 + C[`sp_load] = 1'b0; + // push or sw - write to memory + write = opcode == `OP_PUSH || opcode == `OP_SW; + // pop or lw - read from memory + read = opcode == `OP_POP || opcode == `OP_LW; + end + `PROC_WB: begin + // loaded in previous state, set to 0 + read = 1'b0; + write = 1'b0; + // load now + // pc gets next instruction address + C[`pc_load] = 1'b1; + // sp is decremented after push + C[`sp_load] = opcode == `OP_PUSH; + // write to register file if + // R-type (except jr) or I-type (except beq, bne, sw) or pop or jal + C[`reg_w] = (opcode == `OP_RTYPE && funct != `FN_JR) // R-type (except jr) + || (opcode == `OP_ADDI || opcode == `OP_MULI || opcode == `OP_ANDI || opcode == `OP_ORI + || opcode == `OP_LUI || opcode == `OP_SLTI || opcode == `OP_LW) // I-type (except beq, bne, sw) + || (opcode == `OP_POP || opcode == `OP_JAL) // pop or jal + ; + // pc_sel_2: branch if equal or not equal + C[`pc_sel_2] = ((opcode == `OP_BEQ) && ZERO) || ((opcode == `OP_BNE) && ~ZERO); + end + endcase +end endmodule //------------------------------------------------------------------------------------------ // Module: PROC_SM // Output: STATE : State of the processor -// +// // Input: CLK : Clock signal // RST : Reset signal // // INOUT: MEM_DATA : Data to be read in from or write to the memory // -// Notes: - Processor continuously cycle witnin fetch, decode, execute, +// Notes: - Processor continuously cycle witnin fetch, decode, execute, // memory, write back state. State values are in the prj_definition.v // // Revision History: @@ -56,6 +359,24 @@ input CLK, RST; // list of outputs output [2:0] STATE; -// TBD - take action on each +ve edge of clock +reg [2:0] state_sel = 3'bxxx; -endmodule \ No newline at end of file +always @ (negedge RST) begin + // set to invalid value, so that it defaults to fetch + state_sel = 3'bxxx; +end + +// take action on each +ve edge of clock +always @ (posedge CLK) begin + case (state_sel) + `PROC_FETCH: state_sel = `PROC_DECODE; + `PROC_DECODE: state_sel = `PROC_EXE; + `PROC_EXE: state_sel = `PROC_MEM; + `PROC_MEM: state_sel = `PROC_WB; + `PROC_WB: state_sel = `PROC_FETCH; + default: state_sel = `PROC_FETCH; + endcase +end + +assign STATE = state_sel; +endmodule diff --git a/data_path.v b/data_path.v index 1a03fd3..2c68298 100644 --- a/data_path.v +++ b/data_path.v @@ -17,6 +17,7 @@ //------------------------------------------------------------------------------------------ // `include "prj_definition.v" +`include "control_unit.v" // for control signal index macros module DATA_PATH(DATA_OUT, ADDR, ZERO, INSTRUCTION, DATA_IN, CTRL, CLK, RST); // output list @@ -29,6 +30,102 @@ input [`CTRL_WIDTH_INDEX_LIMIT:0] CTRL; input CLK, RST; input [`DATA_INDEX_LIMIT:0] DATA_IN; -// TBD +// variables +wire [31:0] ir; // Instruction Register +wire [31:0] r1, r2; // Register File +wire [31:0] pc, pc_inc; // Program Counter +wire [31:0] sp; // Stack Pointer +wire [31:0] alu_out; // ALU output + +// instruction sent to control unit +buf ir_buf [31:0] (INSTRUCTION, ir); + +// Parse the instruction data +wire [5:0] opcode; +wire [4:0] rs; +wire [4:0] rt; +wire [4:0] rd; +wire [4:0] shamt; +wire [5:0] funct; +wire [15:0] imm; +wire [25:0] addr; + +// common for all +buf opcode_buf [5:0] (opcode, ir[31:26]); +// common for R-type, I-type +buf rs_buf [4:0] (rs, ir[25:21]); +buf rt_buf [4:0] (rt, ir[20:16]); +// for R-type +buf rd_buf [4:0] (rd, ir[15:11]); +buf shamt_buf [4:0] (shamt, ir[10:6]); +buf funct_buf [5:0] (funct, ir[5:0]); +// for I-type +buf imm_buf [15:0] (imm, ir[15:0]); +// for J-type +buf addr_buf [25:0] (addr, ir[25:0]); + +// Instruction Register +D_LATCH32 ir_inst(.Q(ir), .D(DATA_IN), .LOAD(CTRL[`ir_load]), .RESET(RST)); + +// Register File Input +wire [31:0] r1_sel, wa_sel, wd_sel; +wire [31:0] wa_sel_p1, wa_sel_p2, wd_sel_p1, wd_sel_p2; +wire [31:0] imm_zx_lsb; +buf imm_zx_lsb_buf [31:0] (imm_zx_lsb, {imm, 16'b0}); +MUX32_2x1 mux_r1_sel(r1_sel, {27'b0,rs}, 32'b0, CTRL[`r1_sel_1]); +MUX32_2x1 mux_wa_sel_p1(wa_sel_p1, {27'b0,rd}, {27'b0,rt}, CTRL[`wa_sel_1]); +// 0 for push/pop, 31 for jal +MUX32_2x1 mux_wa_sel_p2(wa_sel_p2, 32'b0, 31, CTRL[`wa_sel_2]); +MUX32_2x1 mux_wa_sel(wa_sel, wa_sel_p2, wa_sel_p1, CTRL[`wa_sel_3]); +MUX32_2x1 mux_wd_sel_p1(wd_sel_p1, alu_out,DATA_IN, CTRL[`wd_sel_1]); +MUX32_2x1 mux_wd_sel_p2(wd_sel_p2, wd_sel_p1, imm_zx_lsb, CTRL[`wd_sel_2]); +MUX32_2x1 mux_wd_sel(wd_sel, pc_inc, wd_sel_p2, CTRL[`wd_sel_3]); +// Register File +REGISTER_FILE_32x32 rf_inst(.DATA_R1(r1), .DATA_R2(r2), .ADDR_R1(r1_sel[4:0]), .ADDR_R2(rt), + .DATA_W(wd_sel), .ADDR_W(wa_sel[4:0]), .READ(CTRL[`reg_r]), .WRITE(CTRL[`reg_w]), + .CLK(CLK), .RST(RST)); + +// ALU Input +wire [31:0] op1_sel, op2_sel; +wire [31:0] op2_sel_p1, op2_sel_p2, op2_sel_p3; +wire [31:0] shamt_zx, imm_sx, imm_zx; +buf shamt_zx_buf [31:0] (shamt_zx, {27'b0, shamt}); +buf imm_sx_buf [31:0] (imm_sx, {{16{imm[15]}}, imm}); +buf imm_zx_buf [31:0] (imm_zx, {16'b0, imm}); +MUX32_2x1 mux_op1_sel(op1_sel, r1, sp, CTRL[`op1_sel_1]); +MUX32_2x1 mux_op2_sel_p1(op2_sel_p1, 32'b1, shamt_zx, CTRL[`op2_sel_1]); +MUX32_2x1 mux_op2_sel_p2(op2_sel_p2, imm_zx, imm_sx, CTRL[`op2_sel_2]); +MUX32_2x1 mux_op2_sel_p3(op2_sel_p3, op2_sel_p2, op2_sel_p1, CTRL[`op2_sel_3]); +MUX32_2x1 mux_op2_sel(op2_sel, op2_sel_p3, r2, CTRL[`op2_sel_4]); +// ALU +ALU alu_inst(.OUT(alu_out), .ZERO(ZERO), .OP1(op1_sel), .OP2(op2_sel), .OPRN(CTRL[`alu_oprn])); + +// Progam Counter Input +wire [31:0] pc_sel; +wire [31:0] pc_branch, pc_jump, pc_sel_p1, pc_sel_p2; +RC_ADD_SUB_32 pc_inc_inst(.Y(pc_inc), .CO(), .A(pc), .B(32'b1), .SnA(1'b0)); +MUX32_2x1 mux_pc_sel_p1(pc_sel_p1, r1, pc_inc, CTRL[`pc_sel_1]); +RC_ADD_SUB_32 pc_sel_2_inst(.Y(pc_branch), .CO(), .A(pc_inc), .B(imm_sx), .SnA(1'b0)); +MUX32_2x1 mux_pc_sel_p2(pc_sel_p2, pc_sel_p1, pc_branch, CTRL[`pc_sel_2]); +buf pc_jump_buf [31:0] (pc_jump, {6'b0, addr}); +MUX32_2x1 mux_pc_sel(pc_sel, pc_jump, pc_sel_p2, CTRL[`pc_sel_3]); +// Program Counter +defparam pc_inst.PATTERN = `INST_START_ADDR; +REG32_PP pc_inst(.Q(pc), .D(pc_sel), .LOAD(CTRL[`pc_load]), .CLK(CLK), .RESET(RST)); + +// Stack Pointer +defparam sp_inst.PATTERN = `INIT_STACK_POINTER; +REG32_PP sp_inst(.Q(sp), .D(alu_out), .LOAD(CTRL[`sp_load]), .CLK(CLK), .RESET(RST)); + +// Data out +MUX32_2x1 mux_data_out(DATA_OUT, r2, r1, CTRL[`md_sel_1]); + +// Address out +wire [31:0] ma_sel_p1; +MUX32_2x1 mux_ma_sel_p1(ma_sel_p1, alu_out, sp, CTRL[`ma_sel_1]); +// discard the upper 6 bits of the address since it's only 26 bit addressable +(* keep="soft" *) +wire [5:0] _addr_ignored; +MUX32_2x1 mux_ma_sel({_addr_ignored,ADDR}, ma_sel_p1, pc, CTRL[`ma_sel_2]); endmodule diff --git a/logic.v b/logic.v index a1b73ad..ddb5567 100644 --- a/logic.v +++ b/logic.v @@ -13,6 +13,23 @@ // 1.0 Sep 02, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation //------------------------------------------------------------------------------------------ // + +// 32-bit D latch +module D_LATCH32(Q, D, LOAD, RESET); +output [31:0] Q; + +input LOAD; +input [31:0] D; +input RESET; + +genvar i; +generate + for (i = 0; i < 32; i = i + 1) begin : d_latch_gen + D_LATCH d_latch_inst(Q[i], _, D[i], LOAD, 1'b1, RESET); + end +endgenerate +endmodule + // 64-bit two's complement module TWOSCOMP64(Y,A); //output list @@ -56,7 +73,6 @@ generate REG1 reg_inst(.Q(Q[i]), .Qbar(qbar[i]), .D(D[i]), .L(LOAD), .C(CLK), .nP(RESET), .nR(1'b1)); end endgenerate - endmodule // 32-bit registere +ve edge, Reset on RESET=0 @@ -73,7 +89,6 @@ generate REG1 r(Q[i], _, D[i], LOAD, CLK, 1'b1, RESET); end endgenerate - endmodule // 1 bit register +ve edge, @@ -164,7 +179,6 @@ generate and msb1(D[i + 16], I[4], half[i]); end endgenerate - endmodule // 4x16 Line decoder @@ -187,8 +201,6 @@ generate and msb1(D[i + 8], I[3], half[i]); end endgenerate - - endmodule // 3x8 Line decoder @@ -211,7 +223,6 @@ generate and msb1(D[i + 4], I[2], half[i]); end endgenerate - endmodule // 2x4 Line decoder diff --git a/prj_definition.v b/prj_definition.v index 540b1c6..eb8cbaa 100644 --- a/prj_definition.v +++ b/prj_definition.v @@ -23,7 +23,7 @@ `define ALU_OPRN_INDEX_LIMIT (`ALU_OPRN_WIDTH -1) `define ADDRESS_WIDTH 26 `define ADDRESS_INDEX_LIMIT (`ADDRESS_WIDTH -1) -`define MEM_SIZE (2 ** `ADDRESS_WIDTH) +`define MEM_SIZE (2 ** (`ADDRESS_WIDTH - 6)) `define MEM_INDEX_LIMIT (`MEM_SIZE - 1) `define NUM_OF_REG 32 `define REG_INDEX_LIMIT (`NUM_OF_REG -1) @@ -41,4 +41,4 @@ // define ISA parameters `define INST_START_ADDR 32'h00001000 -`define INIT_STACK_POINTER 32'h03ffffff +`define INIT_STACK_POINTER 32'h000fffff