diff --git a/logic.v b/logic.v
index 2c0bca2..984a33b 100644
--- a/logic.v
+++ b/logic.v
@@ -20,8 +20,7 @@ output [63:0] Y;
 //input list
 input [63:0] A;
 
-wire _CO;
-RC_ADD_SUB_64 twoscomp64_sub(.Y(Y), .CO(_CO), .A(64'b0), .B(A), .SnA(1'b1));
+RC_ADD_SUB_64 twoscomp64_sub(.Y(Y), .A(64'b0), .B(A), .SnA(1'b1));
 
 endmodule
 
@@ -32,8 +31,7 @@ output [31:0] Y;
 //input list
 input [31:0] A;
 
-wire _CO;
-RC_ADD_SUB_32 twoscomp32_sub(.Y(Y), .CO(_CO), .A(0), .B(A), .SnA(1'b1));
+RC_ADD_SUB_32 twoscomp32_sub(.Y(Y), .A(0), .B(A), .SnA(1'b1));
 
 endmodule