From dbc23d80e484ebbb16985dd1383e8e9cabfd0a2e Mon Sep 17 00:00:00 2001 From: Yuri Tatishchev Date: Thu, 24 Oct 2024 23:11:59 -0700 Subject: [PATCH] lab-08: fix register file - disable writing when WRITE=0 --- TESTBENCH/register_file_tb.v | 1 + register_file.v | 7 +++++-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/TESTBENCH/register_file_tb.v b/TESTBENCH/register_file_tb.v index 20a8117..1690ee5 100644 --- a/TESTBENCH/register_file_tb.v +++ b/TESTBENCH/register_file_tb.v @@ -114,6 +114,7 @@ no_of_pass = no_of_pass + 1; result[ridx] = DATA_R1; ridx=ridx+1; // TODO: Read and write from the same address at the same time? +// TODO: Write when WRITE=0 should be tested #5 READ=1'b0; WRITE=1'b0; // No op diff --git a/register_file.v b/register_file.v index 696bffa..6c6dc05 100644 --- a/register_file.v +++ b/register_file.v @@ -42,8 +42,11 @@ output [`DATA_INDEX_LIMIT:0] DATA_R1; output [`DATA_INDEX_LIMIT:0] DATA_R2; wire [31:0] Q [31:0]; -wire [31:0] r_write; -DECODER_5x32 d_write(r_write, ADDR_W); +wire [31:0] r_write_sel, r_write; +DECODER_5x32 d_write(r_write_sel, ADDR_W); + +// only write when WRITE=1 +and write_active [31:0] (r_write, r_write_sel, WRITE); REG32 r[31:0] (Q, DATA_W, r_write, CLK, RST);