From d1475b5a4f85bc6696b29f40c388bbf8f45a09d8 Mon Sep 17 00:00:00 2001
From: Iurii Tatishchev <itatishch@gmail.com>
Date: Tue, 1 Oct 2024 11:01:17 -0700
Subject: [PATCH] implement a Verilog gate level model for ripple carry adder
 subtractor

Gate level implementation for the following components:
- FULL_ADDER
- HALF_ADDER
- RC_ADD_SUB_32
---
 full_adder.v    | 17 +++++++++++++++--
 half_adder.v    | 10 ++++++++--
 rc_add_sub_32.v | 21 +++++++++++++++++++--
 3 files changed, 42 insertions(+), 6 deletions(-)

diff --git a/full_adder.v b/full_adder.v
index f1f1f83..f1d516f 100644
--- a/full_adder.v
+++ b/full_adder.v
@@ -23,6 +23,19 @@ module FULL_ADDER(S,CO,A,B, CI);
 output S,CO;
 input A,B, CI;
 
-//TBD
+// half adder 1
+//assign Y = A ^ B;
+//assign CO1 = A & B;
 
-endmodule;
+// half adder 2
+//assign S = Y ^ CI;
+//assign CO2 = Y & CI;
+
+//assign CO = CO1 | CO2;
+
+wire Y, CO1, CO2;
+HALF_ADDER ha1(.Y(Y), .C(CO1), .A(A), .B(B));
+HALF_ADDER ha2(.Y(S), .C(CO2), .A(Y), .B(CI));
+assign CO = CO1 | CO2;
+
+endmodule
diff --git a/half_adder.v b/half_adder.v
index 13cc43c..f9ab344 100644
--- a/half_adder.v
+++ b/half_adder.v
@@ -22,6 +22,12 @@ module HALF_ADDER(Y,C,A,B);
 output Y,C;
 input A,B;
 
-// TBD
+// this
+assign Y = A ^ B;
+assign C = A & B;
 
-endmodule;
\ No newline at end of file
+// or this
+//xor digit(Y, A, B);
+//and carry(C, A, B);
+
+endmodule
diff --git a/rc_add_sub_32.v b/rc_add_sub_32.v
index d1a4f08..0fd1e62 100644
--- a/rc_add_sub_32.v
+++ b/rc_add_sub_32.v
@@ -42,7 +42,24 @@ input [`DATA_INDEX_LIMIT:0] A;
 input [`DATA_INDEX_LIMIT:0] B;
 input SnA;
 
-// TBD
+//wire C0, C1, C2, C3;
+//assign C0 = SnA;
+//FULL_ADDER b0(Y[0], C1, A[0], B[0], C0);
+
+// module FULL_ADDER(S,CO,A,B, CI);
+
+// carry-in bits for each 1 bit full adder
+wire C[0:32];
+assign C[0] = SnA;
+
+genvar i;
+generate
+    for (i = 0; i < 32; i = i + 1)
+    begin : add32_gen_loop
+        FULL_ADDER add_inst(Y[i], C[i+1], A[i], B[i] ^ SnA, C[i]);
+    end
+endgenerate
+
+assign CO = C[32];
 
 endmodule
-