From bb7e172316a317167d64c0e032ece8c4ecd936ab Mon Sep 17 00:00:00 2001
From: Yuri Tatishchev <itatishch@gmail.com>
Date: Wed, 2 Oct 2024 16:18:00 -0700
Subject: [PATCH] implement a Verilog gate level model for 64-bit Ripple Carry
 Adder and 32/64-bit twos complement

Gate level implementation for the following components:
- RC_ADD_SUB_64
- TWOSCOMP64
- TWOSCOMP32
---
 logic.v         | 19 +++++++++++++++++--
 rc_add_sub_32.v | 17 ++++++++++++++---
 2 files changed, 31 insertions(+), 5 deletions(-)

diff --git a/logic.v b/logic.v
index 96583f5..0c53ea6 100644
--- a/logic.v
+++ b/logic.v
@@ -20,7 +20,9 @@ output [63:0] Y;
 //input list
 input [63:0] A;
 
-// TBD
+wire _CO;
+
+RC_ADD_SUB_64 twoscomp64_sub(.Y(Y), .CO(_CO), .A(64'b0), .B(A), .SnA(1'b1));
 
 endmodule
 
@@ -31,7 +33,20 @@ output [31:0] Y;
 //input list
 input [31:0] A;
 
-// TBD
+// inverted bits
+// wire A_inv[31:0];
+
+//genvar i;
+//generate
+//    for (i = 0; i < 32; i = i + 1)
+//    begin : inv32_gen_loop
+//        not (A_inv[i], A[i]);
+//    end
+//endgenerate
+
+wire _CO;
+
+RC_ADD_SUB_32 twoscomp32_sub(.Y(Y), .CO(_CO), .A(0), .B(A), .SnA(1'b1));
 
 endmodule
 
diff --git a/rc_add_sub_32.v b/rc_add_sub_32.v
index 03840b4..86cf55b 100644
--- a/rc_add_sub_32.v
+++ b/rc_add_sub_32.v
@@ -29,7 +29,19 @@ input [63:0] A;
 input [63:0] B;
 input SnA;
 
-// TBD
+// carry-in bits for each 1-bit full adder
+wire C[0:64];
+buf (C[0], SnA);
+
+genvar i;
+generate
+    for (i = 0; i < 64; i = i + 1)
+    begin : add64_gen_loop
+        FULL_ADDER add64_inst(Y[i], C[i+1], A[i], B[i] ^ SnA, C[i]);
+    end
+endgenerate
+
+buf (CO, C[64]);
 
 endmodule
 
@@ -50,11 +62,10 @@ genvar i;
 generate
     for (i = 0; i < 32; i = i + 1)
     begin : add32_gen_loop
-        FULL_ADDER add_inst(Y[i], C[i+1], A[i], B[i] ^ SnA, C[i]);
+        FULL_ADDER add32_inst(Y[i], C[i+1], A[i], B[i] ^ SnA, C[i]);
     end
 endgenerate
 
-//assign CO = C[32];
 buf (CO, C[32]);
 
 endmodule