From 8dbdebb9cec9728fb67bd6250c8a51f6f229e951 Mon Sep 17 00:00:00 2001
From: Yuri Tatishchev <itatishch@gmail.com>
Date: Thu, 10 Oct 2024 18:59:09 -0700
Subject: [PATCH] lab-06: gate level model for Arithmetic & Logic Unit

Gate level implementation for the following components:
- ALU
- MUX32_16x1
---
 alu.v | 51 ++++++++++++++++++++++++++++++++++++++++++++++++++-
 mux.v | 21 ---------------------
 2 files changed, 50 insertions(+), 22 deletions(-)

diff --git a/alu.v b/alu.v
index 4262d9c..c4792ea 100644
--- a/alu.v
+++ b/alu.v
@@ -31,7 +31,56 @@ input [`ALU_OPRN_INDEX_LIMIT:0] OPRN; // operation code
 output [`DATA_INDEX_LIMIT:0] OUT; // result of the operation.
 output ZERO;
 
-// TBD
+wire [31:0] res,
+            res_addsub, res_slt,
+            res_shift,
+            res_mul,
+            res_and, res_or, res_nor;
 
+// add = xx0001
+// sub = xx0010
+// slt = xx1001
+//         ^ ^ these bits
+// can use oprn[1] or oprn[3] for SnA
+wire SnA;
+or (SnA, OPRN[1], OPRN[3]);
+RC_ADD_SUB_32 addsub(.Y(res_addsub), .A(OP1), .B(OP2), .SnA(SnA));
+buf slt [31:0] (res_slt, {31'b0,res_addsub[31]});
+
+// shift_r = xx0100
+// shift_l = xx0101
+//                ^ this bit
+// can use oprn[0] for LnR
+SHIFT32 shift(res_shift, OP1, OP2, OPRN[0]);
+
+// mul = xx0011
+MULT32 mul(.LO(res_mul), .A(OP1), .B(OP2));
+
+// and = xx0110
+// or  = xx0111
+// nor = xx1000
+AND32_2x1 and32(res_and, OP1, OP2);
+OR32_2x1 or32(res_or, OP1, OP2);
+NOR32_2x1 nor32(res_nor, OP1, OP2);
+
+MUX32_16x1 out(.Y(res), .S(OPRN[3:0]),
+               .I1(res_addsub), .I2(res_addsub), .I3(res_mul),
+               .I4(res_shift),.I5(res_shift),
+               .I6(res_and), .I7(res_or), .I8(res_nor),
+               .I9(res_slt)
+);
+
+// or bits of result for zero flag
+wire nzf [31:0];
+buf (nzf[0], res[0]);
+genvar i;
+generate
+    for (i = 1; i < 32; i = i + 1) begin : zf_gen
+        or (nzf[i], nzf[i-1], res[i]);
+    end
+endgenerate
+
+not (ZERO, nzf[31]);
+buf res_out [31:0] (OUT, res);
 
 endmodule
diff --git a/mux.v b/mux.v
index f0df2e4..32e7d11 100644
--- a/mux.v
+++ b/mux.v
@@ -96,27 +96,6 @@ input [31:0] I2;
 input [31:0] I3;
 input [1:0] S;
 
-// wire [3:0] x;
-// DECODER_2x4 d(x, S);
-//
-// genvar i;
-// generate
-//     for (i = 0; i < 32; i = i + 1) begin : mux32_4x1_gen
-//         // enabling circuit
-//         wire [3:0] o;
-//         and and0_inst(o[0], x[0], I0[i]);
-//         and and1_inst(o[1], x[1], I1[i]);
-//         and and2_inst(o[2], x[2], I2[i]);
-//         and and3_inst(o[3], x[3], I3[i]);
-//
-//         // combining gate
-//         wire [1:0] p;
-//         or or0(p[0], o[0], o[1]);
-//         or or1(p[1], o[2], o[3]);
-//         or out(Y[i], p[0], p[1]);
-//     end
-// endgenerate
-
 wire [31:0] x0, x1;
 MUX32_2x1 mux2_0(x0, I0, I1, S[0]);
 MUX32_2x1 mux2_1(x1, I2, I3, S[0]);