From 42732e4fe0c2fa5ab6268580bf8ffda98a19d647 Mon Sep 17 00:00:00 2001 From: Iurii Tatishchev Date: Tue, 1 Oct 2024 11:01:17 -0700 Subject: [PATCH] lab-02: gate level model for ripple carry adder subtractor Gate level implementation for the following components: - FULL_ADDER - HALF_ADDER - RC_ADD_SUB_32 --- full_adder.v | 7 +++++-- half_adder.v | 5 +++-- rc_add_sub_32.v | 33 ++++++++++++++++++++++++++++++--- 3 files changed, 38 insertions(+), 7 deletions(-) diff --git a/full_adder.v b/full_adder.v index f1f1f83..1e4d4f0 100644 --- a/full_adder.v +++ b/full_adder.v @@ -23,6 +23,9 @@ module FULL_ADDER(S,CO,A,B, CI); output S,CO; input A,B, CI; -//TBD +wire Y, CO1, CO2; +HALF_ADDER ha1(.Y(Y), .C(CO1), .A(A), .B(B)); +HALF_ADDER ha2(.Y(S), .C(CO2), .A(Y), .B(CI)); +or (CO, CO1, CO2); -endmodule; +endmodule diff --git a/half_adder.v b/half_adder.v index 13cc43c..64e4afb 100644 --- a/half_adder.v +++ b/half_adder.v @@ -22,6 +22,7 @@ module HALF_ADDER(Y,C,A,B); output Y,C; input A,B; -// TBD +xor digit(Y, A, B); +and carry(C, A, B); -endmodule; \ No newline at end of file +endmodule diff --git a/rc_add_sub_32.v b/rc_add_sub_32.v index d1a4f08..5418e4f 100644 --- a/rc_add_sub_32.v +++ b/rc_add_sub_32.v @@ -29,7 +29,21 @@ input [63:0] A; input [63:0] B; input SnA; -// TBD +// carry-in bits for each 1-bit full adder +wire C[0:64]; +buf (C[0], SnA); + +genvar i; +generate + for (i = 0; i < 64; i = i + 1) + begin : add64_gen_loop + wire B_xor; + xor (B_xor, B[i], SnA); + FULL_ADDER add64_inst(Y[i], C[i+1], A[i], B_xor, C[i]); + end +endgenerate + +buf (CO, C[64]); endmodule @@ -42,7 +56,20 @@ input [`DATA_INDEX_LIMIT:0] A; input [`DATA_INDEX_LIMIT:0] B; input SnA; -// TBD +// carry-in bits for each 1-bit full adder +wire C[0:32]; +buf (C[0], SnA); + +genvar i; +generate + for (i = 0; i < 32; i = i + 1) + begin : add32_gen_loop + wire B_xor; + xor (B_xor, B[i], SnA); + FULL_ADDER add32_inst(Y[i], C[i+1], A[i], B_xor, C[i]); + end +endgenerate + +buf (CO, C[32]); endmodule -