From 41ecb62082d1be2a710a8b1bfd69db2b60de63a2 Mon Sep 17 00:00:00 2001
From: Yuri Tatishchev <itatishch@gmail.com>
Date: Sat, 19 Oct 2024 16:05:17 -0700
Subject: [PATCH] lab-07: gate level model for 32-bit register

Gate level implementation for the following components:
- SR_LATCH
- D_LATCH
- D_FF
- REG1
- REG32
---
 logic.v | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/logic.v b/logic.v
index 8a667e4..4db1f09 100644
--- a/logic.v
+++ b/logic.v
@@ -43,7 +43,12 @@ input CLK, LOAD;
 input [31:0] D;
 input RESET;
 
-// TBD
+genvar i;
+generate
+    for (i = 0; i < 32; i = i + 1) begin : reg_gen
+        REG1 r(Q[i], _, D[i], LOAD, CLK, 1'b1, RESET);
+    end
+endgenerate
 
 endmodule