diff --git a/logic.v b/logic.v
index 8a667e4..4db1f09 100644
--- a/logic.v
+++ b/logic.v
@@ -43,7 +43,12 @@ input CLK, LOAD;
 input [31:0] D;
 input RESET;
 
-// TBD
+genvar i;
+generate
+    for (i = 0; i < 32; i = i + 1) begin : reg_gen
+        REG1 r(Q[i], _, D[i], LOAD, CLK, 1'b1, RESET);
+    end
+endgenerate
 
 endmodule