From 171a6d1f775889056dcc714b21aa25f38b5dd7c3 Mon Sep 17 00:00:00 2001
From: Yuri Tatishchev <itatishch@gmail.com>
Date: Thu, 24 Oct 2024 12:33:13 -0700
Subject: [PATCH] lab-08: fix HiZ on register file when READ=0

---
 TESTBENCH/register_file_tb.v | 11 ++++-------
 register_file.v              |  9 ---------
 2 files changed, 4 insertions(+), 16 deletions(-)

diff --git a/TESTBENCH/register_file_tb.v b/TESTBENCH/register_file_tb.v
index 89c8710..20a8117 100644
--- a/TESTBENCH/register_file_tb.v
+++ b/TESTBENCH/register_file_tb.v
@@ -84,7 +84,6 @@ begin
         else
 	    no_of_pass  = no_of_pass + 1;
         result[ridx] = DATA_R1; ridx=ridx+1;
-        // result[ridx] = DATA_R1; ridx=ridx+1;
         
 end
 
@@ -100,21 +99,19 @@ begin
         else
 	    no_of_pass  = no_of_pass + 1;
         result[ridx] = DATA_R1; ridx=ridx+1;
-        // result[ridx] = DATA_R1; ridx=ridx+1;
 
 end
 
 // Test reading when READ=0
 #5     READ=1'b0;
 #5     no_of_test = no_of_test + 1;
-if (DATA_R1 !== 32'bZ)
-        $write("[TEST @ %0dns] READ=0, expecting DATA_R1 to be HiZ, got %8h [FAILED]\n", $time, DATA_R1);
-else if (DATA_R2 !== 32'bZ)
-        $write("[TEST @ %0dns] READ=0, expecting DATA_R2 to be HiZ, got %8h [FAILED]\n", $time, DATA_R2);
+if (DATA_R1 !== 32'bx)
+        $write("[TEST @ %0dns] READ=0, expecting DATA_R1 to be 32{x}, got %8h [FAILED]\n", $time, DATA_R1);
+else if (DATA_R2 !== 32'bx)
+        $write("[TEST @ %0dns] READ=0, expecting DATA_R2 to be 32{x}, got %8h [FAILED]\n", $time, DATA_R2);
 else
 no_of_pass  = no_of_pass + 1;
 result[ridx] = DATA_R1; ridx=ridx+1;
-// result[ridx] = DATA_R1; ridx=ridx+1;
 
 // TODO: Read and write from the same address at the same time?
 
diff --git a/register_file.v b/register_file.v
index ee06ff6..696bffa 100644
--- a/register_file.v
+++ b/register_file.v
@@ -41,14 +41,6 @@ input [`REG_ADDR_INDEX_LIMIT:0] ADDR_R1, ADDR_R2, ADDR_W;
 output [`DATA_INDEX_LIMIT:0] DATA_R1;
 output [`DATA_INDEX_LIMIT:0] DATA_R2;
 
-// module REG32(Q, D, LOAD, CLK, RESET);
-// module DECODER_5x32(D,I);
-
-// module MUX32_32x1(Y, I0, I1, I2, I3, I4, I5, I6, I7,
-                     // I8, I9, I10, I11, I12, I13, I14, I15,
-                     // I16, I17, I18, I19, I20, I21, I22, I23,
-                     // I24, I25, I26, I27, I28, I29, I30, I31, S);
-
 wire [31:0] Q [31:0];
 wire [31:0] r_write;
 DECODER_5x32 d_write(r_write, ADDR_W);
@@ -69,7 +61,6 @@ MUX32_32x1 mux_r2(r2, Q[0], Q[1], Q[2], Q[3], Q[4], Q[5], Q[6], Q[7],
                      ADDR_R2
 );
 
-// TODO: Figure out this high Z thing and add a test for it.
 MUX32_2x1 mux_out1(DATA_R1, {32{1'bZ}}, r1, READ);
 MUX32_2x1 mux_out2(DATA_R2, {32{1'bZ}}, r2, READ);