From 0361dcc1619fd26f1196a7eb182e09e29f72d86b Mon Sep 17 00:00:00 2001 From: Yuri Tatishchev Date: Wed, 20 Nov 2024 01:30:47 -0800 Subject: [PATCH] project: some cleanup --- control_unit.v | 36 ++++++----------- data_path.v | 103 ++++++++++++++----------------------------------- 2 files changed, 40 insertions(+), 99 deletions(-) diff --git a/control_unit.v b/control_unit.v index 46fc853..13f7ec8 100644 --- a/control_unit.v +++ b/control_unit.v @@ -192,7 +192,7 @@ reg [25:0] addr; wire [2:0] state; PROC_SM proc_sm(state, CLK, RST); -// TBD - take action on each +ve edge of clock +// take action on each +ve edge of clock always @ (state) begin // R-type {opcode, rs, rt, rd, shamt, funct} = INSTRUCTION; @@ -201,19 +201,6 @@ always @ (state) begin // J-type {opcode, addr} = INSTRUCTION; - // Print current state -// $write("@ %6dns -> ", $time); -// $write("STATE ", state, ": "); -// case (state) -// `PROC_FETCH: $write("FETCH"); -// `PROC_DECODE: $write("DECODE"); -// `PROC_EXE: $write("EXECUTE"); -// `PROC_MEM: $write("MEMORY"); -// `PROC_WB: $write("WRITE BACK"); -// default: $write("INVALID"); -// endcase -// $write("\n"); - case (state) // fetch - next instruction from memory at PC `PROC_FETCH: begin @@ -222,8 +209,8 @@ always @ (state) begin // memory read = 1'b1; write = 1'b0; - // selections - C[`ma_sel_2] = 1'b1; // load data from mem[PC] + // load data from mem[PC] + C[`ma_sel_2] = 1'b1; end // decode - parse instruction and read values from register file `PROC_DECODE: begin @@ -241,21 +228,21 @@ always @ (state) begin C[`ir_load] = 1'b0; // load now C[`sp_load] = opcode == `OP_POP; // sp is decremented before pop - // selections + // r1_sel_1: rs by default (0), push - r1 (1) C[`r1_sel_1] = opcode == `OP_PUSH; + // wa_sel_1: R-type - write to rd (0), I-type - write to rt (1) C[`wa_sel_1] = opcode != `OP_RTYPE; // wa_sel_2: pop - write to r0 (0), jal - write to r31 (1) C[`wa_sel_2] = opcode == `OP_JAL; - // wa_sel_3: push or pop - wa_sel_2, else wa_sel_1 // wa_sel_3: wa_sel_2 if push or pop or jal (0), else wa_sel_1 (1) C[`wa_sel_3] = ~(opcode == `OP_PUSH || opcode == `OP_POP || opcode == `OP_JAL); + // pc_sel_1: jr - jump to address in rs (0), else pc_inc (1) C[`pc_sel_1] = ~(opcode == `OP_RTYPE && funct == `FN_JR); // pc_sel_2: pc_sel_1 by default (0), beq, bne - branch if equal or not equal (1) - // TODO: this should only be selected if the condition is met - // pc_sel_2 = opcode == `OP_BEQ || opcode == `OP_BNE; + // pc_sel_2 is set after EXE because it depends on ZERO // pc_sel_3: jmp or jal - jump to address (0), else pc_sel_2 (1) C[`pc_sel_3] = ~(opcode == `OP_JMP || opcode == `OP_JAL); @@ -296,31 +283,32 @@ always @ (state) begin end // op1_sel_1: r1 by default (0), push or pop - sp (1) C[`op1_sel_1] = opcode == `OP_PUSH || opcode == `OP_POP; + // op2_sel_1: const 1 (for inc/dec) (0), shamt for sll/srl (1) C[`op2_sel_1] = opcode == `OP_RTYPE && (funct == `FN_SLL || funct == `FN_SRL); // op2_sel_2: imm_zx for logical and/or (0), imm_sx otherise (1) // ('nor' not availble in I-type) C[`op2_sel_2] = ~(opcode == `OP_ANDI || opcode == `OP_ORI); // op2_sel_3: op2_sel_2 for I-type (0), op2_sel_1 for R-type shift or inc/dec (1) - // inc/dec is push or pop + // (inc/dec is for sp with push or pop) C[`op2_sel_3] = opcode == `OP_RTYPE || opcode == `OP_PUSH || opcode == `OP_POP; // op2_sel_4: op2_sel_3 for I-type (except beq, bne) or R-type shift or inc/dec (0), else r2 (1) // i.e. r2 if R-type (except sll/srl), or bne/beq C[`op2_sel_4] = opcode == `OP_RTYPE && ~(funct == `FN_SLL || funct == `FN_SRL) || opcode == `OP_BEQ || opcode == `OP_BNE; - // wd_sel_1: alu_out or DATA_IN // wd_sel_1: alu_out by default (0), DATA_IN for lw or pop (1) C[`wd_sel_1] = opcode == `OP_LW || opcode == `OP_POP; // wd_sel_2: wd_sel_1 by default (0), imm_zx_lsb for lui (1) C[`wd_sel_2] = opcode == `OP_LUI; // wd_sel_3: pc_inc for jal (0), else wd_sel_2 (1) C[`wd_sel_3] = ~(opcode == `OP_JAL); - // ma_sel_1: alu_out for lw or sw, sp for push or pop + // ma_sel_1: alu_out for lw or sw (0), sp for push or pop (1) C[`ma_sel_1] = opcode == `OP_PUSH || opcode == `OP_POP; // ma_sel_2: 0 for every memory access instruction (lw, sw, push, pop), 1 for fetch C[`ma_sel_2] = 1'b0; + // md_sel_1: r2 for sw (0), r1 for push (1) C[`md_sel_1] = opcode == `OP_PUSH; end @@ -387,7 +375,7 @@ always @ (negedge RST) begin state_sel = 3'bxxx; end -// TBD - take action on each +ve edge of clock +// take action on each +ve edge of clock always @ (posedge CLK) begin case (state_sel) `PROC_FETCH: state_sel = `PROC_DECODE; diff --git a/data_path.v b/data_path.v index d87e513..2c68298 100644 --- a/data_path.v +++ b/data_path.v @@ -17,6 +17,7 @@ //------------------------------------------------------------------------------------------ // `include "prj_definition.v" +`include "control_unit.v" // for control signal index macros module DATA_PATH(DATA_OUT, ADDR, ZERO, INSTRUCTION, DATA_IN, CTRL, CLK, RST); // output list @@ -29,53 +30,6 @@ input [`CTRL_WIDTH_INDEX_LIMIT:0] CTRL; input CLK, RST; input [`DATA_INDEX_LIMIT:0] DATA_IN; -wire pc_load, pc_sel_1, pc_sel_2, pc_sel_3, - ir_load, reg_r, reg_w, - r1_sel_1, wa_sel_1, wa_sel_2, wa_sel_3, - - sp_load, op1_sel_1, - op2_sel_1, op2_sel_2, op2_sel_3, op2_sel_4, - - wd_sel_1, wd_sel_2, wd_sel_3, - ma_sel_1, ma_sel_2, - md_sel_1; - -wire [5:0] alu_oprn; - -buf (pc_load, CTRL[0]); -buf (pc_sel_1, CTRL[1]); -buf (pc_sel_2, CTRL[2]); -buf (pc_sel_3, CTRL[3]); - -buf (ir_load, CTRL[4]); - -buf (r1_sel_1, CTRL[5]); -buf (reg_r, CTRL[6]); -buf (reg_w, CTRL[7]); - -buf (sp_load, CTRL[8]); - -buf (op1_sel_1, CTRL[9]); -buf (op2_sel_1, CTRL[10]); -buf (op2_sel_2, CTRL[11]); -buf (op2_sel_3, CTRL[12]); -buf (op2_sel_4, CTRL[13]); - -buf alu_oprn_buf [5:0] (alu_oprn, CTRL[19:14]); - -buf (ma_sel_1, CTRL[20]); -buf (ma_sel_2, CTRL[21]); - -buf (md_sel_1, CTRL[22]); - -buf (wd_sel_1, CTRL[23]); -buf (wd_sel_2, CTRL[24]); -buf (wd_sel_3, CTRL[25]); - -buf (wa_sel_1, CTRL[26]); -buf (wa_sel_2, CTRL[27]); -buf (wa_sel_3, CTRL[28]); - // variables wire [31:0] ir; // Instruction Register wire [31:0] r1, r2; // Register File @@ -83,7 +37,7 @@ wire [31:0] pc, pc_inc; // Program Counter wire [31:0] sp; // Stack Pointer wire [31:0] alu_out; // ALU output -// TODO: Why? +// instruction sent to control unit buf ir_buf [31:0] (INSTRUCTION, ir); // Parse the instruction data @@ -110,27 +64,26 @@ buf imm_buf [15:0] (imm, ir[15:0]); // for J-type buf addr_buf [25:0] (addr, ir[25:0]); - -// Instruction Register input // Instruction Register -D_LATCH32 ir_inst(.Q(ir), .D(DATA_IN), .LOAD(ir_load), .RESET(RST)); +D_LATCH32 ir_inst(.Q(ir), .D(DATA_IN), .LOAD(CTRL[`ir_load]), .RESET(RST)); // Register File Input wire [31:0] r1_sel, wa_sel, wd_sel; wire [31:0] wa_sel_p1, wa_sel_p2, wd_sel_p1, wd_sel_p2; wire [31:0] imm_zx_lsb; buf imm_zx_lsb_buf [31:0] (imm_zx_lsb, {imm, 16'b0}); -MUX32_2x1 mux_r1_sel(r1_sel, {27'b0,rs}, 32'b0, r1_sel_1); -MUX32_2x1 mux_wa_sel_p1(wa_sel_p1, {27'b0,rd}, {27'b0,rt}, wa_sel_1); -// TODO: Why 31? -MUX32_2x1 mux_wa_sel_p2(wa_sel_p2, 32'b0, 31, wa_sel_2); -MUX32_2x1 mux_wa_sel(wa_sel, wa_sel_p2, wa_sel_p1, wa_sel_3); -MUX32_2x1 mux_wd_sel_p1(wd_sel_p1, alu_out,DATA_IN, wd_sel_1); -MUX32_2x1 mux_wd_sel_p2(wd_sel_p2, wd_sel_p1, imm_zx_lsb, wd_sel_2); -MUX32_2x1 mux_wd_sel(wd_sel, pc_inc, wd_sel_p2, wd_sel_3); +MUX32_2x1 mux_r1_sel(r1_sel, {27'b0,rs}, 32'b0, CTRL[`r1_sel_1]); +MUX32_2x1 mux_wa_sel_p1(wa_sel_p1, {27'b0,rd}, {27'b0,rt}, CTRL[`wa_sel_1]); +// 0 for push/pop, 31 for jal +MUX32_2x1 mux_wa_sel_p2(wa_sel_p2, 32'b0, 31, CTRL[`wa_sel_2]); +MUX32_2x1 mux_wa_sel(wa_sel, wa_sel_p2, wa_sel_p1, CTRL[`wa_sel_3]); +MUX32_2x1 mux_wd_sel_p1(wd_sel_p1, alu_out,DATA_IN, CTRL[`wd_sel_1]); +MUX32_2x1 mux_wd_sel_p2(wd_sel_p2, wd_sel_p1, imm_zx_lsb, CTRL[`wd_sel_2]); +MUX32_2x1 mux_wd_sel(wd_sel, pc_inc, wd_sel_p2, CTRL[`wd_sel_3]); // Register File REGISTER_FILE_32x32 rf_inst(.DATA_R1(r1), .DATA_R2(r2), .ADDR_R1(r1_sel[4:0]), .ADDR_R2(rt), - .DATA_W(wd_sel), .ADDR_W(wa_sel[4:0]), .READ(reg_r), .WRITE(reg_w), .CLK(CLK), .RST(RST)); + .DATA_W(wd_sel), .ADDR_W(wa_sel[4:0]), .READ(CTRL[`reg_r]), .WRITE(CTRL[`reg_w]), + .CLK(CLK), .RST(RST)); // ALU Input wire [31:0] op1_sel, op2_sel; @@ -139,40 +92,40 @@ wire [31:0] shamt_zx, imm_sx, imm_zx; buf shamt_zx_buf [31:0] (shamt_zx, {27'b0, shamt}); buf imm_sx_buf [31:0] (imm_sx, {{16{imm[15]}}, imm}); buf imm_zx_buf [31:0] (imm_zx, {16'b0, imm}); -MUX32_2x1 mux_op1_sel(op1_sel, r1, sp, op1_sel_1); -MUX32_2x1 mux_op2_sel_p1(op2_sel_p1, 32'b1, shamt_zx, op2_sel_1); -MUX32_2x1 mux_op2_sel_p2(op2_sel_p2, imm_zx, imm_sx, op2_sel_2); -MUX32_2x1 mux_op2_sel_p3(op2_sel_p3, op2_sel_p2, op2_sel_p1, op2_sel_3); -MUX32_2x1 mux_op2_sel(op2_sel, op2_sel_p3, r2, op2_sel_4); +MUX32_2x1 mux_op1_sel(op1_sel, r1, sp, CTRL[`op1_sel_1]); +MUX32_2x1 mux_op2_sel_p1(op2_sel_p1, 32'b1, shamt_zx, CTRL[`op2_sel_1]); +MUX32_2x1 mux_op2_sel_p2(op2_sel_p2, imm_zx, imm_sx, CTRL[`op2_sel_2]); +MUX32_2x1 mux_op2_sel_p3(op2_sel_p3, op2_sel_p2, op2_sel_p1, CTRL[`op2_sel_3]); +MUX32_2x1 mux_op2_sel(op2_sel, op2_sel_p3, r2, CTRL[`op2_sel_4]); // ALU -ALU alu_inst(.OUT(alu_out), .ZERO(ZERO), .OP1(op1_sel), .OP2(op2_sel), .OPRN(alu_oprn)); +ALU alu_inst(.OUT(alu_out), .ZERO(ZERO), .OP1(op1_sel), .OP2(op2_sel), .OPRN(CTRL[`alu_oprn])); // Progam Counter Input wire [31:0] pc_sel; wire [31:0] pc_branch, pc_jump, pc_sel_p1, pc_sel_p2; RC_ADD_SUB_32 pc_inc_inst(.Y(pc_inc), .CO(), .A(pc), .B(32'b1), .SnA(1'b0)); -MUX32_2x1 mux_pc_sel_p1(pc_sel_p1, r1, pc_inc, pc_sel_1); +MUX32_2x1 mux_pc_sel_p1(pc_sel_p1, r1, pc_inc, CTRL[`pc_sel_1]); RC_ADD_SUB_32 pc_sel_2_inst(.Y(pc_branch), .CO(), .A(pc_inc), .B(imm_sx), .SnA(1'b0)); -MUX32_2x1 mux_pc_sel_p2(pc_sel_p2, pc_sel_p1, pc_branch, pc_sel_2); +MUX32_2x1 mux_pc_sel_p2(pc_sel_p2, pc_sel_p1, pc_branch, CTRL[`pc_sel_2]); buf pc_jump_buf [31:0] (pc_jump, {6'b0, addr}); -MUX32_2x1 mux_pc_sel(pc_sel, pc_jump, pc_sel_p2, pc_sel_3); +MUX32_2x1 mux_pc_sel(pc_sel, pc_jump, pc_sel_p2, CTRL[`pc_sel_3]); // Program Counter defparam pc_inst.PATTERN = `INST_START_ADDR; -REG32_PP pc_inst(.Q(pc), .D(pc_sel), .LOAD(pc_load), .CLK(CLK), .RESET(RST)); +REG32_PP pc_inst(.Q(pc), .D(pc_sel), .LOAD(CTRL[`pc_load]), .CLK(CLK), .RESET(RST)); // Stack Pointer defparam sp_inst.PATTERN = `INIT_STACK_POINTER; -REG32_PP sp_inst(.Q(sp), .D(alu_out), .LOAD(sp_load), .CLK(CLK), .RESET(RST)); +REG32_PP sp_inst(.Q(sp), .D(alu_out), .LOAD(CTRL[`sp_load]), .CLK(CLK), .RESET(RST)); // Data out -MUX32_2x1 mux_data_out(DATA_OUT, r2, r1, md_sel_1); +MUX32_2x1 mux_data_out(DATA_OUT, r2, r1, CTRL[`md_sel_1]); // Address out wire [31:0] ma_sel_p1; -MUX32_2x1 mux_ma_sel_p1(ma_sel_p1, alu_out, sp, ma_sel_1); -// TODO: Check address calculation since it's 26 bit +MUX32_2x1 mux_ma_sel_p1(ma_sel_p1, alu_out, sp, CTRL[`ma_sel_1]); +// discard the upper 6 bits of the address since it's only 26 bit addressable (* keep="soft" *) wire [5:0] _addr_ignored; -MUX32_2x1 mux_ma_sel({_addr_ignored,ADDR}, ma_sel_p1, pc, ma_sel_2); +MUX32_2x1 mux_ma_sel({_addr_ignored,ADDR}, ma_sel_p1, pc, CTRL[`ma_sel_2]); endmodule